intel/nir: Clean up lower_alpha_to_coverage a bit

[mesa.git] / src / intel / blorp / blorp.h

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index ead261b6230cdf6a8e89bde7477d54efd169a2c0..b88178266c387ab2a9c5cb5869539b728a1d65ef 100644 (file)
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -49,6 +49,7 @@ struct blorp_context {
                          const void *key, uint32_t key_size,
                          uint32_t *kernel_out, void *prog_data_out);
    bool (*upload_shader)(struct blorp_batch *batch,
+                         uint32_t stage,
                          const void *key, uint32_t key_size,
                          const void *kernel, uint32_t kernel_size,
                          const struct brw_stage_prog_data *prog_data,
@@ -160,12 +161,10 @@ blorp_buffer_copy(struct blorp_batch *batch,
                   struct blorp_address dst,
                   uint64_t size);
 
-union isl_color_value
-swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle);
-
 void
 blorp_fast_clear(struct blorp_batch *batch,
-                 const struct blorp_surf *surf, enum isl_format format,
+                 const struct blorp_surf *surf,
+                 enum isl_format format, struct isl_swizzle swizzle,
                  uint32_t level, uint32_t start_layer, uint32_t num_layers,
                  uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1);
 
@@ -246,6 +245,10 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
              uint32_t level, uint32_t start_layer, uint32_t num_layers,
              enum isl_aux_op op);
 
+void
+blorp_hiz_stencil_op(struct blorp_batch *batch, struct blorp_surf *stencil,
+                     uint32_t level, uint32_t start_layer,
+                     uint32_t num_layers, enum isl_aux_op op);
 #ifdef __cplusplus
 } /* end extern "C" */
 #endif /* __cplusplus */