pan/bi: Flesh out st_vary IR

[mesa.git] / src / intel / common / gen_l3_config.c

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index e0825e92d9fa99a257bb46a89ca8e798753049f3..46926f8bdf4952a435bddf9ad3fcddeff5c96d98 100644 (file)
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -101,6 +101,61 @@ static const struct gen_l3_config chv_l3_configs[] = {
    {{ 0 }}
 };
 
+/**
+ * BXT 2x6 validated L3 configurations.  \sa ivb_l3_configs.
+ */
+static const struct gen_l3_config bxt_2x6_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   {{  0, 32, 48,  0,  0,  0,  0,  0 }},
+   {{  0, 32,  0,  8, 40,  0,  0,  0 }},
+   {{  0, 32,  0, 32, 16,  0,  0,  0 }},
+   {{ 16, 16, 48,  0,  0,  0,  0,  0 }},
+   {{ 16, 16,  0, 40,  8,  0,  0,  0 }},
+   {{ 16, 16,  0, 16, 32,  0,  0,  0 }},
+   {{ 0 }}
+};
+
+/**
+ * CNL validated L3 configurations.  \sa ivb_l3_configs.
+ */
+static const struct gen_l3_config cnl_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
+   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
+   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
+   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
+   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
+   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
+   {{ 32, 16, 80,  0,  0,  0,  0,  0 }},
+   {{ 32, 16,  0, 64, 16,  0,  0,  0 }},
+   {{ 32,  0, 96,  0,  0,  0,  0,  0 }},
+   {{ 0 }}
+};
+
+/**
+ * ICL validated L3 configurations.  \sa icl_l3_configs.
+ * Zeroth entry in below table has been commented out intentionally
+ * due to known issues with this configuration. Many other entries
+ * suggested by h/w specification aren't added here because they
+ * do under allocation of L3 cache with below partitioning.
+ */
+static const struct gen_l3_config icl_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   /*{{  0, 16, 80,  0,  0,  0,  0,  0 }},*/
+   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
+   {{  0 }}
+};
+
+/**
+ * TGL validated L3 configurations.  \sa tgl_l3_configs.
+ */
+static const struct gen_l3_config tgl_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   {{  0, 32,  88,  0,  0,  0,  0,  0 }},
+   {{  0, 16, 104,  0,  0,  0,  0,  0 }},
+   {{  0 }}
+};
+
 /**
  * Return a zero-terminated array of validated L3 configurations for the
  * specified device.
@@ -116,8 +171,19 @@ get_l3_configs(const struct gen_device_info *devinfo)
       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 
    case 9:
+      if (devinfo->l3_banks == 1)
+         return bxt_2x6_l3_configs;
       return chv_l3_configs;
 
+   case 10:
+      return cnl_l3_configs;
+
+   case 11:
+      return icl_l3_configs;
+
+   case 12:
+      return tgl_l3_configs;
+
    default:
       unreachable("Not implemented");
    }
@@ -196,7 +262,7 @@ gen_get_default_l3_weights(const struct gen_device_info *devinfo,
 {
    struct gen_l3_weights w = {{ 0 }};
 
-   w.w[GEN_L3P_SLM] = needs_slm;
+   w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
    w.w[GEN_L3P_URB] = 1.0;
 
    if (devinfo->gen >= 8) {
@@ -254,8 +320,12 @@ gen_get_l3_config(const struct gen_device_info *devinfo,
 static unsigned
 get_l3_way_size(const struct gen_device_info *devinfo)
 {
+   const unsigned way_size_per_bank =
+      (devinfo->gen >= 9 && devinfo->l3_banks == 1) || devinfo->gen >= 11 ?
+      4 : 2;
+
    assert(devinfo->l3_banks);
-   return 2 * devinfo->l3_banks;
+   return way_size_per_bank * devinfo->l3_banks;
 }
 
 /**