nir: Replace the scoped_memory barrier by a scoped_barrier

[mesa.git] / src / intel / compiler / brw_compiler.c

diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index 626ff4bb16aaab322f166dd751371d3d9df86716..c26b6eb3bbca0a5e86f103cba9d8e31571553fcb 100644 (file)
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -34,9 +34,7 @@
    .lower_fdiv = true,                                                        \
    .lower_scmp = true,                                                        \
    .lower_flrp16 = true,                                                      \
-   .lower_fmod16 = true,                                                      \
-   .lower_fmod32 = true,                                                      \
-   .lower_fmod64 = false,                                                     \
+   .lower_fmod = true,                                                        \
    .lower_bitfield_extract = true,                                            \
    .lower_bitfield_insert = true,                                             \
    .lower_uadd_carry = true,                                                  \
@@ -46,11 +44,16 @@
    .lower_isign = true,                                                       \
    .lower_ldexp = true,                                                       \
    .lower_device_index_to_zero = true,                                        \
+   .vectorize_io = true,                                                      \
    .use_interpolated_input_intrinsics = true,                                 \
    .vertex_id_zero_based = true,                                              \
-   .lower_base_vertex = true
+   .lower_base_vertex = true,                                                 \
+   .use_scoped_barrier = true,                                                \
+   .support_8bit_alu = true,                                                  \
+   .support_16bit_alu = true
 
 #define COMMON_SCALAR_OPTIONS                                                 \
+   .lower_to_scalar = true,                                                   \
    .lower_pack_half_2x16 = true,                                              \
    .lower_pack_snorm_2x16 = true,                                             \
    .lower_pack_snorm_4x8 = true,                                              \
@@ -61,6 +64,9 @@
    .lower_unpack_snorm_4x8 = true,                                            \
    .lower_unpack_unorm_2x16 = true,                                           \
    .lower_unpack_unorm_4x8 = true,                                            \
+   .lower_usub_sat64 = true,                                                  \
+   .lower_hadd64 = true,                                                      \
+   .lower_bfe_with_two_constants = true,                                      \
    .max_unroll_iterations = 32
 
 static const struct nir_shader_compiler_options scalar_nir_options = {
@@ -83,6 +89,7 @@ static const struct nir_shader_compiler_options vector_nir_options = {
    .lower_unpack_unorm_2x16 = true,
    .lower_extract_byte = true,
    .lower_extract_word = true,
+   .intel_vec4 = true,
    .max_unroll_iterations = 32,
 };
 
@@ -99,6 +106,10 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 
    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 
+   compiler->use_tcs_8_patch =
+      devinfo->gen >= 12 ||
+      (devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
+
    if (devinfo->gen >= 10) {
       /* We don't support vec4 mode on Cannonlake. */
       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
@@ -130,9 +141,11 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
       nir_lower_dceil |
       nir_lower_dfract |
       nir_lower_dround_even |
-      nir_lower_dmod;
+      nir_lower_dmod |
+      nir_lower_dsub |
+      nir_lower_ddiv;
 
-   if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) {
+   if (!devinfo->has_64bit_float || (INTEL_DEBUG & DEBUG_SOFT64)) {
       int64_options |= nir_lower_mov64 |
                        nir_lower_icmp64 |
                        nir_lower_iadd64 |
@@ -140,7 +153,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
                        nir_lower_ineg64 |
                        nir_lower_logic64 |
                        nir_lower_minmax64 |
-                       nir_lower_shift64;
+                       nir_lower_shift64 |
+                       nir_lower_extract64;
       fp64_options |= nir_lower_fp64_full_software;
    }
 
@@ -179,9 +193,16 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
        */
       nir_options->lower_ffma = devinfo->gen < 6;
       nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
+      nir_options->lower_fpow = devinfo->gen >= 12;
+
+      nir_options->lower_rotate = devinfo->gen < 11;
+      nir_options->lower_bitfield_reverse = devinfo->gen < 7;
 
       nir_options->lower_int64_options = int64_options;
       nir_options->lower_doubles_options = fp64_options;
+
+      nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
+
       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 
       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;