intel: Rewrite the world of push/pull params

[mesa.git] / src / intel / compiler / brw_compiler.h

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 038f3f95512d2ab820e16dc5a669506e28f4d9ee..f2f9be750a0620c445879ccbb9ed83995d49de23 100644 (file)
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -36,7 +36,6 @@ extern "C" {
 struct ra_regs;
 struct nir_shader;
 struct brw_program;
-union gl_constant_value;
 
 struct brw_compiler {
    const struct gen_device_info *devinfo;
@@ -491,6 +490,66 @@ struct brw_ubo_range
    uint8_t length;
 };
 
+/* We reserve the first 2^16 values for builtins */
+#define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
+
+enum brw_param_builtin {
+   BRW_PARAM_BUILTIN_ZERO,
+
+   BRW_PARAM_BUILTIN_CLIP_PLANE_0_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_0_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_1_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_1_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_2_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_2_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_3_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_3_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_4_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_4_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_5_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_5_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_6_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_6_W,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_7_X,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z,
+   BRW_PARAM_BUILTIN_CLIP_PLANE_7_W,
+
+   BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X,
+   BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y,
+   BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z,
+   BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W,
+   BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
+   BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
+};
+
+#define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
+   (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
+
+#define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param)  \
+   ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
+    (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
+
+#define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
+   (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
+
+#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
+   (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
+
 struct brw_stage_prog_data {
    struct {
       /** size of our binding table. */
@@ -529,11 +588,14 @@ struct brw_stage_prog_data {
 
    bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
 
-   /* Pointers to tracked values (only valid once
-    * _mesa_load_state_parameters has been called at runtime).
+   /* 32-bit identifiers for all push/pull parameters.  These can be anything
+    * the driver wishes them to be; the core of the back-end compiler simply
+    * re-arranges them.  The one restriction is that the bottom 2^16 values
+    * are reserved for builtins defined in the brw_param_builtin enum defined
+    * above.
     */
-   const union gl_constant_value **param;
-   const union gl_constant_value **pull_param;
+   uint32_t *param;
+   uint32_t *pull_param;
 
    /** Image metadata passed to the shader as uniforms. */
    struct brw_image_param *image_param;
@@ -1020,7 +1082,6 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
                const struct brw_vs_prog_key *key,
                struct brw_vs_prog_data *prog_data,
                const struct nir_shader *shader,
-               gl_clip_plane *clip_planes,
                bool use_legacy_snorm_formula,
                int shader_time_index,
                unsigned *final_assembly_size,