intel/compiler: Enable the emission of ROR/ROL instructions

[mesa.git] / src / intel / compiler / brw_eu_defines.h

diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 933037c4df3519aef8ce63ce26aa074d108a2aa3..e8ca7ff8b98e7ecb2effcc0561b9c564c462c12a 100644 (file)
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -210,7 +210,9 @@ enum opcode {
    BRW_OPCODE_SMOV =   10,  /**< Gen8+       */ /* Reused */
    /* Reserved - 11 */
    BRW_OPCODE_ASR =    12,
-   /* Reserved - 13-15 */
+   /* Reserved - 13 */
+   BRW_OPCODE_ROR =    14,  /**< Gen11+ */
+   BRW_OPCODE_ROL =    15,  /**< Gen11+ */
    BRW_OPCODE_CMP =    16,
    BRW_OPCODE_CMPN =   17,
    BRW_OPCODE_CSEL =   18,  /**< Gen8+ */