intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.

[mesa.git] / src / intel / compiler / brw_eu_validate.c

diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index 9b31b99ed2b49a088b48f89123e8dcd8ee534c7d..d0a5ca9e203cbebebe9b2234e89d96d45dbe2f1d 100644 (file)
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -310,6 +310,8 @@ inst_uses_src_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
    case BRW_OPCODE_MACH:
    case BRW_OPCODE_SADA2:
       return true;
+   default:
+      break;
    }
 
    /* FIXME: support 3-src instructions */
@@ -389,7 +391,7 @@ static bool
 is_unsupported_inst(const struct gen_device_info *devinfo,
                     const brw_inst *inst)
 {
-   return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
+   return brw_inst_opcode(devinfo, inst) == BRW_OPCODE_ILLEGAL;
 }
 
 /**