}
}
+static bool
+inst_is_split_send(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ switch (brw_inst_opcode(devinfo, inst)) {
+ case BRW_OPCODE_SENDS:
+ case BRW_OPCODE_SENDSC:
+ return true;
+ default:
+ return false;
+ }
+}
+
static unsigned
signed_type(unsigned type)
{
if (num_sources == 3)
return (struct string){};
+ /* Nothing to test. Split sends can only encode a file in sources that are
+ * allowed to be NULL.
+ */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
if (num_sources >= 1)
ERROR_IF(src0_is_null(devinfo, inst), "src0 is null");
{
struct string error_msg = { .str = NULL, .len = 0 };
- if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
+ if (inst_is_split_send(devinfo, inst)) {
+ ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
+ brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL,
+ "src1 of split send must be a GRF or NULL");
+
+ ERROR_IF(brw_inst_eot(devinfo, inst) &&
+ brw_inst_src0_da_reg_nr(devinfo, inst) < 112,
+ "send with EOT must use g112-g127");
+ ERROR_IF(brw_inst_eot(devinfo, inst) &&
+ brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE &&
+ brw_inst_send_src1_reg_nr(devinfo, inst) < 112,
+ "send with EOT must use g112-g127");
+
+ if (brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) {
+ /* Assume minimums if we don't know */
+ unsigned mlen = 1;
+ if (!brw_inst_send_sel_reg32_desc(devinfo, inst)) {
+ const uint32_t desc = brw_inst_send_desc(devinfo, inst);
+ mlen = brw_message_desc_mlen(devinfo, desc);
+ }
+
+ unsigned ex_mlen = 1;
+ if (!brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) {
+ const uint32_t ex_desc = brw_inst_send_ex_desc(devinfo, inst);
+ ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc);
+ }
+ const unsigned src0_reg_nr = brw_inst_src0_da_reg_nr(devinfo, inst);
+ const unsigned src1_reg_nr = brw_inst_send_src1_reg_nr(devinfo, inst);
+ ERROR_IF((src0_reg_nr <= src1_reg_nr &&
+ src1_reg_nr < src0_reg_nr + mlen) ||
+ (src1_reg_nr <= src0_reg_nr &&
+ src0_reg_nr < src1_reg_nr + ex_mlen),
+ "split send payloads must not overlap");
+ }
+ } else if (inst_is_send(devinfo, inst)) {
ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT,
"send must use direct addressing");
return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
}
+/**
+ * Returns whether a combination of two types would qualify as mixed float
+ * operation mode
+ */
+static inline bool
+types_are_mixed_float(enum brw_reg_type t0, enum brw_reg_type t1)
+{
+ return (t0 == BRW_REGISTER_TYPE_F && t1 == BRW_REGISTER_TYPE_HF) ||
+ (t1 == BRW_REGISTER_TYPE_F && t0 == BRW_REGISTER_TYPE_HF);
+}
+
static enum brw_reg_type
execution_type_for_type(enum brw_reg_type type)
{
enum brw_reg_type src0_exec_type, src1_exec_type;
/* Execution data type is independent of destination data type, except in
- * mixed F/HF instructions on CHV and SKL+.
+ * mixed F/HF instructions.
*/
enum brw_reg_type dst_exec_type = brw_inst_dst_type(devinfo, inst);
src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst));
if (num_sources == 1) {
- if ((devinfo->gen >= 9 || devinfo->is_cherryview) &&
- src0_exec_type == BRW_REGISTER_TYPE_HF) {
+ if (src0_exec_type == BRW_REGISTER_TYPE_HF)
return dst_exec_type;
- }
return src0_exec_type;
}
src1_exec_type = execution_type_for_type(brw_inst_src1_type(devinfo, inst));
+ if (types_are_mixed_float(src0_exec_type, src1_exec_type) ||
+ types_are_mixed_float(src0_exec_type, dst_exec_type) ||
+ types_are_mixed_float(src1_exec_type, dst_exec_type)) {
+ return BRW_REGISTER_TYPE_F;
+ }
+
if (src0_exec_type == src1_exec_type)
return src0_exec_type;
src1_exec_type == BRW_REGISTER_TYPE_DF)
return BRW_REGISTER_TYPE_DF;
- if (devinfo->gen >= 9 || devinfo->is_cherryview) {
- if (dst_exec_type == BRW_REGISTER_TYPE_F ||
- src0_exec_type == BRW_REGISTER_TYPE_F ||
- src1_exec_type == BRW_REGISTER_TYPE_F) {
- return BRW_REGISTER_TYPE_F;
- } else {
- return BRW_REGISTER_TYPE_HF;
- }
- }
-
- assert(src0_exec_type == BRW_REGISTER_TYPE_F);
- return BRW_REGISTER_TYPE_F;
+ unreachable("not reached");
}
/**
return false;
}
+/**
+ * Returns whether an instruction is an explicit or implicit conversion
+ * to/from half-float.
+ */
+static bool
+is_half_float_conversion(const struct gen_device_info *devinfo,
+ const brw_inst *inst)
+{
+ enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+
+ unsigned num_sources = num_sources_from_inst(devinfo, inst);
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+
+ if (dst_type != src0_type &&
+ (dst_type == BRW_REGISTER_TYPE_HF || src0_type == BRW_REGISTER_TYPE_HF)) {
+ return true;
+ } else if (num_sources > 1) {
+ enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
+ return dst_type != src1_type &&
+ (dst_type == BRW_REGISTER_TYPE_HF ||
+ src1_type == BRW_REGISTER_TYPE_HF);
+ }
+
+ return false;
+}
+
+/*
+ * Returns whether an instruction is using mixed float operation mode
+ */
+static bool
+is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ if (devinfo->gen < 8)
+ return false;
+
+ if (inst_is_send(devinfo, inst))
+ return false;
+
+ unsigned opcode = brw_inst_opcode(devinfo, inst);
+ const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+ if (desc->ndst == 0)
+ return false;
+
+ /* FIXME: support 3-src instructions */
+ unsigned num_sources = num_sources_from_inst(devinfo, inst);
+ assert(num_sources < 3);
+
+ enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+
+ if (num_sources == 1)
+ return types_are_mixed_float(src0_type, dst_type);
+
+ enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
+
+ return types_are_mixed_float(src0_type, src1_type) ||
+ types_are_mixed_float(src0_type, dst_type) ||
+ types_are_mixed_float(src1_type, dst_type);
+}
+
/**
* Checks restrictions listed in "General Restrictions Based on Operand Types"
* in the "Register Region Restrictions" section.
exec_type_size == 8 && dst_type_size == 4)
dst_type_size = 8;
- if (exec_type_size > dst_type_size) {
+ if (is_half_float_conversion(devinfo, inst)) {
+ /**
+ * A helper to validate used in the validation of the following restriction
+ * from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
+ *
+ * "There is no direct conversion from HF to DF or DF to HF.
+ * There is no direct conversion from HF to Q/UQ or Q/UQ to HF."
+ *
+ * Even if these restrictions are listed for the MOV instruction, we
+ * validate this more generally, since there is the possibility
+ * of implicit conversions from other instructions, such us implicit
+ * conversion from integer to HF with the ADD instruction in SKL+.
+ */
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+ enum brw_reg_type src1_type = num_sources > 1 ?
+ brw_inst_src1_type(devinfo, inst) : 0;
+ ERROR_IF(dst_type == BRW_REGISTER_TYPE_HF &&
+ (type_sz(src0_type) == 8 ||
+ (num_sources > 1 && type_sz(src1_type) == 8)),
+ "There are no direct conversions between 64-bit types and HF");
+
+ ERROR_IF(type_sz(dst_type) == 8 &&
+ (src0_type == BRW_REGISTER_TYPE_HF ||
+ (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)),
+ "There are no direct conversions between 64-bit types and HF");
+
+ /* From the BDW+ PRM:
+ *
+ * "Conversion between Integer and HF (Half Float) must be
+ * DWord-aligned and strided by a DWord on the destination."
+ *
+ * Also, the above restrictions seems to be expanded on CHV and SKL+ by:
+ *
+ * "There is a relaxed alignment rule for word destinations. When
+ * the destination type is word (UW, W, HF), destination data types
+ * can be aligned to either the lowest word or the second lowest
+ * word of the execution channel. This means the destination data
+ * words can be either all in the even word locations or all in the
+ * odd word locations."
+ *
+ * We do not implement the second rule as is though, since empirical
+ * testing shows inconsistencies:
+ * - It suggests that packed 16-bit is not allowed, which is not true.
+ * - It suggests that conversions from Q/DF to W (which need to be
+ * 64-bit aligned on the destination) are not possible, which is
+ * not true.
+ *
+ * So from this rule we only validate the implication that conversions
+ * from F to HF need to be DWord strided (except in Align1 mixed
+ * float mode where packed fp16 destination is allowed so long as the
+ * destination is oword-aligned).
+ *
+ * Finally, we only validate this for Align1 because Align16 always
+ * requires packed destinations, so these restrictions can't possibly
+ * apply to Align16 mode.
+ */
+ if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
+ if ((dst_type == BRW_REGISTER_TYPE_HF &&
+ (brw_reg_type_is_integer(src0_type) ||
+ (num_sources > 1 && brw_reg_type_is_integer(src1_type)))) ||
+ (brw_reg_type_is_integer(dst_type) &&
+ (src0_type == BRW_REGISTER_TYPE_HF ||
+ (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)))) {
+ ERROR_IF(dst_stride * dst_type_size != 4,
+ "Conversions between integer and half-float must be "
+ "strided by a DWord on the destination");
+
+ unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+ ERROR_IF(subreg % 4 != 0,
+ "Conversions between integer and half-float must be "
+ "aligned to a DWord on the destination");
+ } else if ((devinfo->is_cherryview || devinfo->gen >= 9) &&
+ dst_type == BRW_REGISTER_TYPE_HF) {
+ unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+ ERROR_IF(dst_stride != 2 &&
+ !(is_mixed_float(devinfo, inst) &&
+ dst_stride == 1 && subreg % 16 == 0),
+ "Conversions to HF must have either all words in even "
+ "word locations or all words in odd word locations or "
+ "be mixed-float with Oword-aligned packed destination");
+ }
+ }
+ }
+
+ /* There are special regioning rules for mixed-float mode in CHV and SKL that
+ * override the general rule for the ratio of sizes of the destination type
+ * and the execution type. We will add validation for those in a later patch.
+ */
+ bool validate_dst_size_and_exec_size_ratio =
+ !is_mixed_float(devinfo, inst) ||
+ !(devinfo->is_cherryview || devinfo->gen >= 9);
+
+ if (validate_dst_size_and_exec_size_ratio &&
+ exec_type_size > dst_type_size) {
if (!(dst_type_is_byte && inst_is_raw_move(devinfo, inst))) {
ERROR_IF(dst_stride * dst_type_size != exec_type_size,
"Destination stride must be equal to the ratio of the sizes "
if (num_sources == 3)
return (struct string){};
+ /* Split sends don't have the bits in the instruction to encode regions so
+ * there's nothing to check.
+ */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) {
if (desc->ndst != 0 && !dst_is_null(devinfo, inst))
ERROR_IF(brw_inst_dst_hstride(devinfo, inst) != BRW_HORIZONTAL_STRIDE_1,
if (num_sources == 3 || num_sources == 0)
return (struct string){};
+ /* Split sends don't have types so there's no doubles there. */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
enum brw_reg_type exec_type = execution_type(devinfo, inst);
unsigned exec_type_size = brw_reg_type_to_size(exec_type);
projects / mesa.git / blobdiff