/*
- * Copyright © 2015 Intel Corporation
+ * Copyright © 2015-2019 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
/** @file brw_eu_validate.c
*
* This file implements a pass that validates shader assembly.
+ *
+ * The restrictions implemented herein are intended to verify that instructions
+ * in shader assembly do not violate restrictions documented in the graphics
+ * programming reference manuals.
+ *
+ * The restrictions are difficult for humans to quickly verify due to their
+ * complexity and abundance.
+ *
+ * It is critical that this code is thoroughly unit tested because false
+ * results will lead developers astray, which is worse than having no validator
+ * at all. Functional changes to this file without corresponding unit tests (in
+ * test_eu_validate.cpp) will be rejected.
*/
#include "brw_eu.h"
}
#define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
+static bool
+contains(const struct string haystack, const struct string needle)
+{
+ return haystack.str && memmem(haystack.str, haystack.len,
+ needle.str, needle.len) != NULL;
+}
+#define CONTAINS(haystack, needle) \
+ contains(haystack, (struct string){needle, strlen(needle)})
+
#define error(str) "\tERROR: " str "\n"
#define ERROR_INDENT "\t "
#define ERROR(msg) ERROR_IF(true, msg)
-#define ERROR_IF(cond, msg) \
- do { \
- if (cond) { \
- CAT(error_msg, error(msg)); \
- } \
+#define ERROR_IF(cond, msg) \
+ do { \
+ if ((cond) && !CONTAINS(error_msg, error(msg))) { \
+ CAT(error_msg, error(msg)); \
+ } \
} while(0)
#define CHECK(func, args...) \
} \
} while (0)
+#define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
+#define WIDTH(width) (1 << (width))
+
static bool
inst_is_send(const struct gen_device_info *devinfo, const brw_inst *inst)
{
}
}
+static bool
+inst_is_split_send(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ switch (brw_inst_opcode(devinfo, inst)) {
+ case BRW_OPCODE_SENDS:
+ case BRW_OPCODE_SENDSC:
+ return true;
+ default:
+ return false;
+ }
+}
+
static unsigned
signed_type(unsigned type)
{
if (num_sources == 3)
return (struct string){};
+ /* Nothing to test. Split sends can only encode a file in sources that are
+ * allowed to be NULL.
+ */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
if (num_sources >= 1)
ERROR_IF(src0_is_null(devinfo, inst), "src0 is null");
{
struct string error_msg = { .str = NULL, .len = 0 };
- if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
+ if (inst_is_split_send(devinfo, inst)) {
+ ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
+ brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL,
+ "src1 of split send must be a GRF or NULL");
+
+ ERROR_IF(brw_inst_eot(devinfo, inst) &&
+ brw_inst_src0_da_reg_nr(devinfo, inst) < 112,
+ "send with EOT must use g112-g127");
+ ERROR_IF(brw_inst_eot(devinfo, inst) &&
+ brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE &&
+ brw_inst_send_src1_reg_nr(devinfo, inst) < 112,
+ "send with EOT must use g112-g127");
+
+ if (brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) {
+ /* Assume minimums if we don't know */
+ unsigned mlen = 1;
+ if (!brw_inst_send_sel_reg32_desc(devinfo, inst)) {
+ const uint32_t desc = brw_inst_send_desc(devinfo, inst);
+ mlen = brw_message_desc_mlen(devinfo, desc);
+ }
+
+ unsigned ex_mlen = 1;
+ if (!brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) {
+ const uint32_t ex_desc = brw_inst_send_ex_desc(devinfo, inst);
+ ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc);
+ }
+ const unsigned src0_reg_nr = brw_inst_src0_da_reg_nr(devinfo, inst);
+ const unsigned src1_reg_nr = brw_inst_send_src1_reg_nr(devinfo, inst);
+ ERROR_IF((src0_reg_nr <= src1_reg_nr &&
+ src1_reg_nr < src0_reg_nr + mlen) ||
+ (src1_reg_nr <= src0_reg_nr &&
+ src0_reg_nr < src1_reg_nr + ex_mlen),
+ "split send payloads must not overlap");
+ }
+ } else if (inst_is_send(devinfo, inst)) {
ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT,
"send must use direct addressing");
brw_inst_src0_da_reg_nr(devinfo, inst) < 112,
"send with EOT must use g112-g127");
}
+
+ if (devinfo->gen >= 8) {
+ ERROR_IF(!dst_is_null(devinfo, inst) &&
+ (brw_inst_dst_da_reg_nr(devinfo, inst) +
+ brw_inst_rlen(devinfo, inst) > 127) &&
+ (brw_inst_src0_da_reg_nr(devinfo, inst) +
+ brw_inst_mlen(devinfo, inst) >
+ brw_inst_dst_da_reg_nr(devinfo, inst)),
+ "r127 must not be used for return address when there is "
+ "a src and dest overlap");
+ }
}
return error_msg;
return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
}
+/**
+ * Returns whether a combination of two types would qualify as mixed float
+ * operation mode
+ */
+static inline bool
+types_are_mixed_float(enum brw_reg_type t0, enum brw_reg_type t1)
+{
+ return (t0 == BRW_REGISTER_TYPE_F && t1 == BRW_REGISTER_TYPE_HF) ||
+ (t1 == BRW_REGISTER_TYPE_F && t0 == BRW_REGISTER_TYPE_HF);
+}
+
static enum brw_reg_type
execution_type_for_type(enum brw_reg_type type)
{
switch (type) {
+ case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
enum brw_reg_type src0_exec_type, src1_exec_type;
/* Execution data type is independent of destination data type, except in
- * mixed F/HF instructions on CHV and SKL+.
+ * mixed F/HF instructions.
*/
enum brw_reg_type dst_exec_type = brw_inst_dst_type(devinfo, inst);
src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst));
if (num_sources == 1) {
- if ((devinfo->gen >= 9 || devinfo->is_cherryview) &&
- src0_exec_type == BRW_REGISTER_TYPE_HF) {
+ if (src0_exec_type == BRW_REGISTER_TYPE_HF)
return dst_exec_type;
- }
return src0_exec_type;
}
src1_exec_type = execution_type_for_type(brw_inst_src1_type(devinfo, inst));
+ if (types_are_mixed_float(src0_exec_type, src1_exec_type) ||
+ types_are_mixed_float(src0_exec_type, dst_exec_type) ||
+ types_are_mixed_float(src1_exec_type, dst_exec_type)) {
+ return BRW_REGISTER_TYPE_F;
+ }
+
if (src0_exec_type == src1_exec_type)
return src0_exec_type;
src1_exec_type == BRW_REGISTER_TYPE_DF)
return BRW_REGISTER_TYPE_DF;
- if (devinfo->gen >= 9 || devinfo->is_cherryview) {
- if (dst_exec_type == BRW_REGISTER_TYPE_F ||
- src0_exec_type == BRW_REGISTER_TYPE_F ||
- src1_exec_type == BRW_REGISTER_TYPE_F) {
- return BRW_REGISTER_TYPE_F;
- } else {
- return BRW_REGISTER_TYPE_HF;
- }
- }
-
- assert(src0_exec_type == BRW_REGISTER_TYPE_F);
- return BRW_REGISTER_TYPE_F;
+ unreachable("not reached");
}
/**
return false;
}
+/**
+ * Returns whether an instruction is an explicit or implicit conversion
+ * to/from half-float.
+ */
+static bool
+is_half_float_conversion(const struct gen_device_info *devinfo,
+ const brw_inst *inst)
+{
+ enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+
+ unsigned num_sources = num_sources_from_inst(devinfo, inst);
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+
+ if (dst_type != src0_type &&
+ (dst_type == BRW_REGISTER_TYPE_HF || src0_type == BRW_REGISTER_TYPE_HF)) {
+ return true;
+ } else if (num_sources > 1) {
+ enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
+ return dst_type != src1_type &&
+ (dst_type == BRW_REGISTER_TYPE_HF ||
+ src1_type == BRW_REGISTER_TYPE_HF);
+ }
+
+ return false;
+}
+
+/*
+ * Returns whether an instruction is using mixed float operation mode
+ */
+static bool
+is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ if (devinfo->gen < 8)
+ return false;
+
+ if (inst_is_send(devinfo, inst))
+ return false;
+
+ unsigned opcode = brw_inst_opcode(devinfo, inst);
+ const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+ if (desc->ndst == 0)
+ return false;
+
+ /* FIXME: support 3-src instructions */
+ unsigned num_sources = num_sources_from_inst(devinfo, inst);
+ assert(num_sources < 3);
+
+ enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+
+ if (num_sources == 1)
+ return types_are_mixed_float(src0_type, dst_type);
+
+ enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
+
+ return types_are_mixed_float(src0_type, src1_type) ||
+ types_are_mixed_float(src0_type, dst_type) ||
+ types_are_mixed_float(src1_type, dst_type);
+}
+
/**
* Checks restrictions listed in "General Restrictions Based on Operand Types"
* in the "Register Region Restrictions" section.
* In fact, checking it would weaken testing of the other rules.
*/
- unsigned dst_stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
+ unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
bool dst_type_is_byte =
brw_inst_dst_type(devinfo, inst) == BRW_REGISTER_TYPE_B ||
exec_type_size == 8 && dst_type_size == 4)
dst_type_size = 8;
- if (exec_type_size > dst_type_size) {
- ERROR_IF(dst_stride * dst_type_size != exec_type_size,
- "Destination stride must be equal to the ratio of the sizes of "
- "the execution data type to the destination type");
+ if (is_half_float_conversion(devinfo, inst)) {
+ /**
+ * A helper to validate used in the validation of the following restriction
+ * from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
+ *
+ * "There is no direct conversion from HF to DF or DF to HF.
+ * There is no direct conversion from HF to Q/UQ or Q/UQ to HF."
+ *
+ * Even if these restrictions are listed for the MOV instruction, we
+ * validate this more generally, since there is the possibility
+ * of implicit conversions from other instructions, such us implicit
+ * conversion from integer to HF with the ADD instruction in SKL+.
+ */
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+ enum brw_reg_type src1_type = num_sources > 1 ?
+ brw_inst_src1_type(devinfo, inst) : 0;
+ ERROR_IF(dst_type == BRW_REGISTER_TYPE_HF &&
+ (type_sz(src0_type) == 8 ||
+ (num_sources > 1 && type_sz(src1_type) == 8)),
+ "There are no direct conversions between 64-bit types and HF");
+
+ ERROR_IF(type_sz(dst_type) == 8 &&
+ (src0_type == BRW_REGISTER_TYPE_HF ||
+ (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)),
+ "There are no direct conversions between 64-bit types and HF");
+
+ /* From the BDW+ PRM:
+ *
+ * "Conversion between Integer and HF (Half Float) must be
+ * DWord-aligned and strided by a DWord on the destination."
+ *
+ * Also, the above restrictions seems to be expanded on CHV and SKL+ by:
+ *
+ * "There is a relaxed alignment rule for word destinations. When
+ * the destination type is word (UW, W, HF), destination data types
+ * can be aligned to either the lowest word or the second lowest
+ * word of the execution channel. This means the destination data
+ * words can be either all in the even word locations or all in the
+ * odd word locations."
+ *
+ * We do not implement the second rule as is though, since empirical
+ * testing shows inconsistencies:
+ * - It suggests that packed 16-bit is not allowed, which is not true.
+ * - It suggests that conversions from Q/DF to W (which need to be
+ * 64-bit aligned on the destination) are not possible, which is
+ * not true.
+ *
+ * So from this rule we only validate the implication that conversions
+ * from F to HF need to be DWord strided (except in Align1 mixed
+ * float mode where packed fp16 destination is allowed so long as the
+ * destination is oword-aligned).
+ *
+ * Finally, we only validate this for Align1 because Align16 always
+ * requires packed destinations, so these restrictions can't possibly
+ * apply to Align16 mode.
+ */
+ if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
+ if ((dst_type == BRW_REGISTER_TYPE_HF &&
+ (brw_reg_type_is_integer(src0_type) ||
+ (num_sources > 1 && brw_reg_type_is_integer(src1_type)))) ||
+ (brw_reg_type_is_integer(dst_type) &&
+ (src0_type == BRW_REGISTER_TYPE_HF ||
+ (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)))) {
+ ERROR_IF(dst_stride * dst_type_size != 4,
+ "Conversions between integer and half-float must be "
+ "strided by a DWord on the destination");
+
+ unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+ ERROR_IF(subreg % 4 != 0,
+ "Conversions between integer and half-float must be "
+ "aligned to a DWord on the destination");
+ } else if ((devinfo->is_cherryview || devinfo->gen >= 9) &&
+ dst_type == BRW_REGISTER_TYPE_HF) {
+ unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+ ERROR_IF(dst_stride != 2 &&
+ !(is_mixed_float(devinfo, inst) &&
+ dst_stride == 1 && subreg % 16 == 0),
+ "Conversions to HF must have either all words in even "
+ "word locations or all words in odd word locations or "
+ "be mixed-float with Oword-aligned packed destination");
+ }
+ }
+ }
+
+ /* There are special regioning rules for mixed-float mode in CHV and SKL that
+ * override the general rule for the ratio of sizes of the destination type
+ * and the execution type. We will add validation for those in a later patch.
+ */
+ bool validate_dst_size_and_exec_size_ratio =
+ !is_mixed_float(devinfo, inst) ||
+ !(devinfo->is_cherryview || devinfo->gen >= 9);
+
+ if (validate_dst_size_and_exec_size_ratio &&
+ exec_type_size > dst_type_size) {
+ if (!(dst_type_is_byte && inst_is_raw_move(devinfo, inst))) {
+ ERROR_IF(dst_stride * dst_type_size != exec_type_size,
+ "Destination stride must be equal to the ratio of the sizes "
+ "of the execution data type to the destination type");
+ }
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
if (num_sources == 3)
return (struct string){};
+ /* Split sends don't have the bits in the instruction to encode regions so
+ * there's nothing to check.
+ */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) {
if (desc->ndst != 0 && !dst_is_null(devinfo, inst))
ERROR_IF(brw_inst_dst_hstride(devinfo, inst) != BRW_HORIZONTAL_STRIDE_1,
BRW_IMMEDIATE_VALUE) \
continue; \
\
- vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
- width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
- hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
+ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
+ width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
+ hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
type = brw_inst_src ## n ## _type(devinfo, inst); \
element_size = brw_reg_type_to_size(type); \
subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
BRW_IMMEDIATE_VALUE) \
continue; \
\
- vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
- width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
- hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
+ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
+ width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
+ hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
type = brw_inst_src ## n ## _type(devinfo, inst); \
element_size = brw_reg_type_to_size(type); \
subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
if (desc->ndst == 0 || dst_is_null(devinfo, inst))
return error_msg;
- unsigned stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
+ unsigned stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
unsigned element_size = brw_reg_type_to_size(dst_type);
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
} \
} \
\
- ERROR_IF(offset_0 != offset_1, \
+ ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
"The offset from the two source registers " \
"must be the same")
for (unsigned i = 0; i < num_sources; i++) {
#define DO_SRC(n) \
unsigned vstride, width, hstride; \
- vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
- width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
- hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
- (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
+ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
+ width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
+ hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
bool src ## n ## _is_packed_word = \
is_packed(vstride, width, hstride) && \
(brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
unsigned dst_type_size = brw_reg_type_to_size(dst_type);
unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ?
brw_inst_dst_da1_subreg_nr(devinfo, inst) : 0;
- unsigned dst_stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
+ unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
enum brw_reg_type type = num_sources == 1 ?
brw_inst_src0_type(devinfo, inst) :
brw_inst_src1_type(devinfo, inst);
return error_msg;
}
+static struct string
+special_requirements_for_handling_double_precision_data_types(
+ const struct gen_device_info *devinfo,
+ const brw_inst *inst)
+{
+ unsigned num_sources = num_sources_from_inst(devinfo, inst);
+ struct string error_msg = { .str = NULL, .len = 0 };
+
+ if (num_sources == 3 || num_sources == 0)
+ return (struct string){};
+
+ /* Split sends don't have types so there's no doubles there. */
+ if (inst_is_split_send(devinfo, inst))
+ return (struct string){};
+
+ enum brw_reg_type exec_type = execution_type(devinfo, inst);
+ unsigned exec_type_size = brw_reg_type_to_size(exec_type);
+
+ enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, inst);
+ enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+ unsigned dst_type_size = brw_reg_type_to_size(dst_type);
+ unsigned dst_hstride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
+ unsigned dst_reg = brw_inst_dst_da_reg_nr(devinfo, inst);
+ unsigned dst_subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+ unsigned dst_address_mode = brw_inst_dst_address_mode(devinfo, inst);
+
+ bool is_integer_dword_multiply =
+ devinfo->gen >= 8 &&
+ brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL &&
+ (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
+ brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) &&
+ (brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
+ brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_UD);
+
+ if (dst_type_size != 8 && exec_type_size != 8 && !is_integer_dword_multiply)
+ return (struct string){};
+
+ for (unsigned i = 0; i < num_sources; i++) {
+ unsigned vstride, width, hstride, type_size, reg, subreg, address_mode;
+ bool is_scalar_region;
+ enum brw_reg_file file;
+ enum brw_reg_type type;
+
+#define DO_SRC(n) \
+ if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
+ BRW_IMMEDIATE_VALUE) \
+ continue; \
+ \
+ is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
+ vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
+ width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
+ hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
+ file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
+ type = brw_inst_src ## n ## _type(devinfo, inst); \
+ type_size = brw_reg_type_to_size(type); \
+ reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
+ subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
+ address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
+
+ if (i == 0) {
+ DO_SRC(0);
+ } else {
+ DO_SRC(1);
+ }
+#undef DO_SRC
+
+ /* The PRMs say that for CHV, BXT:
+ *
+ * When source or destination datatype is 64b or operation is integer
+ * DWord multiply, regioning in Align1 must follow these rules:
+ *
+ * 1. Source and Destination horizontal stride must be aligned to the
+ * same qword.
+ * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
+ * 3. Source and Destination offset must be the same, except the case
+ * of scalar source.
+ *
+ * We assume that the restriction applies to GLK as well.
+ */
+ if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
+ (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
+ unsigned src_stride = hstride * type_size;
+ unsigned dst_stride = dst_hstride * dst_type_size;
+
+ ERROR_IF(!is_scalar_region &&
+ (src_stride % 8 != 0 ||
+ dst_stride % 8 != 0 ||
+ src_stride != dst_stride),
+ "Source and destination horizontal stride must equal and a "
+ "multiple of a qword when the execution type is 64-bit");
+
+ ERROR_IF(vstride != width * hstride,
+ "Vstride must be Width * Hstride when the execution type is "
+ "64-bit");
+
+ ERROR_IF(!is_scalar_region && dst_subreg != subreg,
+ "Source and destination offset must be the same when the "
+ "execution type is 64-bit");
+ }
+
+ /* The PRMs say that for CHV, BXT:
+ *
+ * When source or destination datatype is 64b or operation is integer
+ * DWord multiply, indirect addressing must not be used.
+ *
+ * We assume that the restriction applies to GLK as well.
+ */
+ if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
+ ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode ||
+ BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode,
+ "Indirect addressing is not allowed when the execution type "
+ "is 64-bit");
+ }
+
+ /* The PRMs say that for CHV, BXT:
+ *
+ * ARF registers must never be used with 64b datatype or when
+ * operation is integer DWord multiply.
+ *
+ * We assume that the restriction applies to GLK as well.
+ *
+ * We assume that the restriction does not apply to the null register.
+ */
+ if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
+ ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC ||
+ brw_inst_acc_wr_control(devinfo, inst) ||
+ (BRW_ARCHITECTURE_REGISTER_FILE == file &&
+ reg != BRW_ARF_NULL) ||
+ (BRW_ARCHITECTURE_REGISTER_FILE == dst_file &&
+ dst_reg != BRW_ARF_NULL),
+ "Architecture registers cannot be used when the execution "
+ "type is 64-bit");
+ }
+ }
+
+ /* The PRMs say that for BDW, SKL:
+ *
+ * If Align16 is required for an operation with QW destination and non-QW
+ * source datatypes, the execution size cannot exceed 2.
+ *
+ * We assume that the restriction applies to all Gen8+ parts.
+ */
+ if (devinfo->gen >= 8) {
+ enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
+ enum brw_reg_type src1_type =
+ num_sources > 1 ? brw_inst_src1_type(devinfo, inst) : src0_type;
+ unsigned src0_type_size = brw_reg_type_to_size(src0_type);
+ unsigned src1_type_size = brw_reg_type_to_size(src1_type);
+
+ ERROR_IF(brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16 &&
+ dst_type_size == 8 &&
+ (src0_type_size != 8 || src1_type_size != 8) &&
+ brw_inst_exec_size(devinfo, inst) > BRW_EXECUTE_2,
+ "In Align16 exec size cannot exceed 2 with a QWord destination "
+ "and a non-QWord source");
+ }
+
+ /* The PRMs say that for CHV, BXT:
+ *
+ * When source or destination datatype is 64b or operation is integer
+ * DWord multiply, DepCtrl must not be used.
+ *
+ * We assume that the restriction applies to GLK as well.
+ */
+ if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
+ ERROR_IF(brw_inst_no_dd_check(devinfo, inst) ||
+ brw_inst_no_dd_clear(devinfo, inst),
+ "DepCtrl is not allowed when the execution type is 64-bit");
+ }
+
+ return error_msg;
+}
+
bool
brw_validate_instructions(const struct gen_device_info *devinfo,
- void *assembly, int start_offset, int end_offset,
- struct annotation_info *annotation)
+ const void *assembly, int start_offset, int end_offset,
+ struct disasm_info *disasm)
{
bool valid = true;
CHECK(general_restrictions_on_region_parameters);
CHECK(region_alignment_rules);
CHECK(vector_immediate_restrictions);
+ CHECK(special_requirements_for_handling_double_precision_data_types);
}
- if (error_msg.str && annotation) {
- annotation_insert_error(annotation, src_offset, error_msg.str);
+ if (error_msg.str && disasm) {
+ disasm_insert_error(disasm, src_offset, error_msg.str);
}
valid = valid && error_msg.len == 0;
free(error_msg.str);
projects / mesa.git / blobdiff