intel/fs: Drop all of the 64-bit varying code
[mesa.git] / src / intel / compiler / brw_fs.h
index 73aebbcfb22d38fbf1dd5d87b0f09d5823e49ea0..1dde4c9c7d2c37bea376bbeeb2d55ca7c0b68c40 100644 (file)
@@ -52,6 +52,11 @@ offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
 
 #define UBO_START ((1 << 16) - 4)
 
+struct shader_stats {
+   const char *scheduler_mode;
+   unsigned promoted_constants;
+};
+
 /**
  * The fragment shader front-end.
  *
@@ -62,7 +67,7 @@ class fs_visitor : public backend_shader
 public:
    fs_visitor(const struct brw_compiler *compiler, void *log_data,
               void *mem_ctx,
-              const void *key,
+              const brw_base_prog_key *key,
               struct brw_stage_prog_data *prog_data,
               struct gl_program *prog,
               const nir_shader *shader,
@@ -80,8 +85,6 @@ public:
 
    fs_reg vgrf(const glsl_type *const type);
    void import_uniforms(fs_visitor *v);
-   void setup_uniform_clipplane_values();
-   void compute_clip_distance();
 
    void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
                                    const fs_reg &dst,
@@ -92,7 +95,7 @@ public:
 
    bool run_fs(bool allow_spilling, bool do_rep_send);
    bool run_vs();
-   bool run_tcs_single_patch();
+   bool run_tcs();
    bool run_tes();
    bool run_gs();
    bool run_cs(unsigned min_dispatch_width);
@@ -106,21 +109,16 @@ public:
    bool fixup_sends_duplicate_payload();
    void fixup_3src_null_dest();
    void assign_curb_setup();
-   void calculate_urb_setup();
    void assign_urb_setup();
    void convert_attr_sources_to_hw_regs(fs_inst *inst);
    void assign_vs_urb_setup();
-   void assign_tcs_single_patch_urb_setup();
+   void assign_tcs_urb_setup();
    void assign_tes_urb_setup();
    void assign_gs_urb_setup();
    bool assign_regs(bool allow_spilling, bool spill_all);
    void assign_regs_trivial();
    void calculate_payload_ranges(int payload_node_count,
                                  int *payload_last_use_ip);
-   void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
-                                   int first_payload_node);
-   int choose_spill_reg(struct ra_graph *g);
-   void spill_reg(unsigned spill_reg);
    void split_virtual_grfs();
    bool compact_virtual_grfs();
    void assign_constant_locations();
@@ -183,10 +181,13 @@ public:
    void emit_interpolation_setup_gen6();
    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
    fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
-                         const fs_reg &sampler);
+                         const fs_reg &texture,
+                         const fs_reg &texture_handle);
    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
    fs_reg resolve_source_modifiers(const fs_reg &src);
    void emit_discard_jump();
+   void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
+                   fs_reg result, fs_reg *op, unsigned fsign_src);
    bool opt_peephole_sel();
    bool opt_peephole_csel();
    bool opt_peephole_predicated_break();
@@ -194,6 +195,8 @@ public:
    bool opt_cmod_propagation();
    bool opt_zero_samples();
 
+   void set_tcs_invocation_id();
+
    void emit_nir_code();
    void nir_setup_outputs();
    void nir_setup_uniforms();
@@ -204,7 +207,10 @@ public:
    void nir_emit_loop(nir_loop *loop);
    void nir_emit_block(nir_block *block);
    void nir_emit_instr(nir_instr *instr);
-   void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
+   void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
+                     bool need_dest);
+   bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
+                              nir_alu_instr *instr);
    void nir_emit_load_const(const brw::fs_builder &bld,
                             nir_load_const_instr *instr);
    void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
@@ -245,6 +251,12 @@ public:
    fs_reg get_nir_src_imm(const nir_src &src);
    fs_reg get_nir_dest(const nir_dest &dest);
    fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
+   fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
+                                          nir_intrinsic_instr *instr);
+   fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
+                                         nir_intrinsic_instr *instr);
+   struct brw_reg get_tcs_output_urb_handle();
+
    void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
                      unsigned wr_mask);
 
@@ -257,6 +269,7 @@ public:
    fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
                                  fs_reg color1, fs_reg color2,
                                  fs_reg src0_alpha, unsigned components);
+   void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha);
    void emit_fb_writes();
    fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
                                       const fs_reg &dst, unsigned target);
@@ -293,7 +306,7 @@ public:
    void dump_instruction(backend_instruction *inst);
    void dump_instruction(backend_instruction *inst, FILE *file);
 
-   const void *const key;
+   const brw_base_prog_key *const key;
    const struct brw_sampler_prog_key_data *key_tex;
 
    struct brw_gs_compile *gs_compile;
@@ -369,7 +382,6 @@ public:
    fs_reg pixel_w;
    fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
    fs_reg shader_start_time;
-   fs_reg userplane[MAX_CLIP_PLANES];
    fs_reg final_gs_vertex_count;
    fs_reg control_data_bits;
    fs_reg invocation_id;
@@ -382,8 +394,18 @@ public:
 
    int shader_time_index;
 
-   unsigned promoted_constants;
+   struct shader_stats shader_stats;
+
    brw::fs_builder bld;
+
+private:
+   fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
+                                              nir_alu_instr *instr,
+                                              fs_reg *op,
+                                              bool need_dest);
+
+   void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
+                             fs_reg *op);
 };
 
 /**
@@ -397,7 +419,7 @@ public:
    fs_generator(const struct brw_compiler *compiler, void *log_data,
                 void *mem_ctx,
                 struct brw_stage_prog_data *prog_data,
-                unsigned promoted_constants,
+                struct shader_stats shader_stats,
                 bool runtime_check_aads_emit,
                 gl_shader_stage stage);
    ~fs_generator();
@@ -501,7 +523,7 @@ private:
    unsigned dispatch_width; /**< 8, 16 or 32 */
 
    exec_list discard_halt_patches;
-   unsigned promoted_constants;
+   struct shader_stats shader_stats;
    bool runtime_check_aads_emit;
    bool debug_flag;
    const char *shader_name;
@@ -550,11 +572,6 @@ void shuffle_from_32bit_read(const brw::fs_builder &bld,
                              uint32_t first_component,
                              uint32_t components);
 
-fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld,
-                               const fs_reg &src,
-                               uint32_t first_component,
-                               uint32_t components);
-
 fs_reg setup_imm_df(const brw::fs_builder &bld,
                     double v);