i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions

[mesa.git] / src / intel / compiler / brw_fs.h

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 00861ce5dad772465d6132626873d943350ee2de..e230b5e0dd920b1103b727bdbdda31200717c1b5 100644 (file)
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -25,7 +25,8 @@
  *
  */
 
-#pragma once
+#ifndef BRW_FS_H
+#define BRW_FS_H
 
 #include "brw_shader.h"
 #include "brw_ir_fs.h"
@@ -160,7 +161,7 @@ public:
    void lower_uniform_pull_constant_loads();
    bool lower_load_payload();
    bool lower_pack();
-   bool lower_d2x();
+   bool lower_conversions();
    bool lower_logical_sends();
    bool lower_integer_multiplication();
    bool lower_minmax();
@@ -498,3 +499,5 @@ fs_reg setup_imm_df(const brw::fs_builder &bld,
 
 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
                                                nir_intrinsic_op op);
+
+#endif /* BRW_FS_H */