nir: Add bit_count to lower_int64 pass

[mesa.git] / src / intel / compiler / brw_fs_bank_conflicts.cpp

diff --git a/src/intel/compiler/brw_fs_bank_conflicts.cpp b/src/intel/compiler/brw_fs_bank_conflicts.cpp
index f10caf249d0f51cce35c6e7fd8f620fc8f859975..ec19dc6160b9838b0a38e0d2fb3b94e70419a68e 100644 (file)
--- a/src/intel/compiler/brw_fs_bank_conflicts.cpp
+++ b/src/intel/compiler/brw_fs_bank_conflicts.cpp
@@ -935,20 +935,16 @@ fs_visitor::opt_bank_conflicts()
 }
 
 /**
- * Estimate the number of GRF bank conflict cycles incurred by an instruction.
+ * Return whether the instruction incurs GRF bank conflict cycles.
  *
- * Note that this neglects conflict cycles prior to register allocation
- * because we don't know which bank each VGRF is going to end up aligned to.
+ * Note that this is only accurate after register allocation because otherwise
+ * we don't know which bank each VGRF is going to end up aligned to.
  */
-unsigned
-fs_visitor::bank_conflict_cycles(const fs_inst *inst) const
+bool
+has_bank_conflict(const gen_device_info *devinfo, const fs_inst *inst)
 {
-   if (grf_used && inst->is_3src(devinfo) &&
-       is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
-       bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
-       !is_conflict_optimized_out(devinfo, inst)) {
-      return DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
-   } else {
-      return 0;
-   }
+   return inst->is_3src(devinfo) &&
+          is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
+          bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
+          !is_conflict_optimized_out(devinfo, inst);
 }