* Alias for group() with width equal to eight.
*/
fs_builder
- half(unsigned i) const
+ quarter(unsigned i) const
{
return group(8, i);
}
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
}
- /**
- * Get the mask of SIMD channels enabled by dispatch and not yet
- * disabled by discard.
- */
- src_reg
- sample_mask_reg() const
- {
- if (shader->stage != MESA_SHADER_FRAGMENT) {
- return brw_imm_d(0xffffffff);
- } else if (brw_wm_prog_data(shader->stage_prog_data)->uses_kill) {
- return brw_flag_reg(0, 1);
- } else {
- assert(shader->devinfo->gen >= 6 && dispatch_width() <= 16);
- return retype(brw_vec1_grf((_group >= 16 ? 2 : 1), 7),
- BRW_REGISTER_TYPE_UD);
- }
- }
-
/**
* Insert an instruction into the program.
*/
case SHADER_OPCODE_INT_REMAINDER:
return emit(instruction(opcode, dispatch_width(), dst,
fix_math_operand(src0),
- fix_math_operand(src1)));
+ fix_math_operand(fix_byte_src(src1))));
default:
- return emit(instruction(opcode, dispatch_width(), dst, src0, src1));
+ return emit(instruction(opcode, dispatch_width(), dst,
+ src0, fix_byte_src(src1)));
}
}
case BRW_OPCODE_LRP:
return emit(instruction(opcode, dispatch_width(), dst,
fix_3src_operand(src0),
- fix_3src_operand(src1),
- fix_3src_operand(src2)));
+ fix_3src_operand(fix_byte_src(src1)),
+ fix_3src_operand(fix_byte_src(src2))));
default:
return emit(instruction(opcode, dispatch_width(), dst,
- src0, src1, src2));
+ src0, fix_byte_src(src1), fix_byte_src(src2)));
}
}
emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[],
unsigned n) const
{
- return emit(instruction(opcode, dispatch_width(), dst, srcs, n));
+ /* Use the emit() methods for specific operand counts to ensure that
+ * opcode-specific operand fixups occur.
+ */
+ if (n == 2) {
+ return emit(opcode, dst, srcs[0], srcs[1]);
+ } else if (n == 3) {
+ return emit(opcode, dst, srcs[0], srcs[1], srcs[2]);
+ } else {
+ return emit(instruction(opcode, dispatch_width(), dst, srcs, n));
+ }
}
/**
{
assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
- return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
- fix_unsigned_negate(src1)));
+ /* In some cases we can't have bytes as operand for src1, so use the
+ * same type for both operand.
+ */
+ return set_condmod(mod, SEL(dst, fix_unsigned_negate(fix_byte_src(src0)),
+ fix_unsigned_negate(fix_byte_src(src1))));
}
/**
const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
const dst_reg dst = vgrf(src.type);
- ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index)->flag_subreg = 2;
+ ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
return src_reg(component(dst, 0));
}
+ src_reg
+ move_to_vgrf(const src_reg &src, unsigned num_components) const
+ {
+ src_reg *const src_comps = new src_reg[num_components];
+ for (unsigned i = 0; i < num_components; i++)
+ src_comps[i] = offset(src, dispatch_width(), i);
+
+ const dst_reg dst = vgrf(src.type, num_components);
+ LOAD_PAYLOAD(dst, src_comps, num_components, 0);
+
+ delete[] src_comps;
+
+ return src_reg(dst);
+ }
+
void
emit_scan(enum opcode opcode, const dst_reg &tmp,
unsigned cluster_size, brw_conditional_mod mod) const
if (cluster_size > 1) {
const fs_builder ubld = exec_all().group(dispatch_width() / 2, 0);
- dst_reg left = horiz_stride(tmp, 2);
- dst_reg right = horiz_stride(horiz_offset(tmp, 1), 2);
-
- /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
- *
- * "When source or destination datatype is 64b or operation is
- * integer DWord multiply, regioning in Align1 must follow
- * these rules:
- *
- * [...]
- *
- * 3. Source and Destination offset must be the same, except
- * the case of scalar source."
- *
- * In order to work around this, we create a temporary register
- * and shift left over to match right. If we have a 64-bit type,
- * we have to use two integer MOVs instead of a 64-bit MOV.
- */
- if (need_matching_subreg_offset(opcode, tmp.type)) {
- dst_reg tmp2 = vgrf(tmp.type);
- dst_reg new_left = horiz_stride(horiz_offset(tmp2, 1), 2);
- if (type_sz(tmp.type) > 4) {
- ubld.MOV(subscript(new_left, BRW_REGISTER_TYPE_D, 0),
- subscript(left, BRW_REGISTER_TYPE_D, 0));
- ubld.MOV(subscript(new_left, BRW_REGISTER_TYPE_D, 1),
- subscript(left, BRW_REGISTER_TYPE_D, 1));
- } else {
- ubld.MOV(new_left, left);
- }
- left = new_left;
- }
+ const dst_reg left = horiz_stride(tmp, 2);
+ const dst_reg right = horiz_stride(horiz_offset(tmp, 1), 2);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
if (cluster_size > 2) {
- if (type_sz(tmp.type) <= 4 &&
- !need_matching_subreg_offset(opcode, tmp.type)) {
+ if (type_sz(tmp.type) <= 4) {
const fs_builder ubld =
exec_all().group(dispatch_width() / 4, 0);
src_reg left = horiz_stride(horiz_offset(tmp, 1), 4);
}
}
- if (cluster_size > 4) {
- const fs_builder ubld = exec_all().group(4, 0);
- src_reg left = component(tmp, 3);
- dst_reg right = horiz_offset(tmp, 4);
+ for (unsigned i = 4;
+ i < MIN2(cluster_size, dispatch_width());
+ i *= 2) {
+ const fs_builder ubld = exec_all().group(i, 0);
+ src_reg left = component(tmp, i - 1);
+ dst_reg right = horiz_offset(tmp, i);
set_condmod(mod, ubld.emit(opcode, right, left, right));
- if (dispatch_width() > 8) {
- left = component(tmp, 8 + 3);
- right = horiz_offset(tmp, 8 + 4);
+ if (dispatch_width() > i * 2) {
+ left = component(tmp, i * 3 - 1);
+ right = horiz_offset(tmp, i * 3);
set_condmod(mod, ubld.emit(opcode, right, left, right));
}
- }
- if (cluster_size > 8 && dispatch_width() > 8) {
- const fs_builder ubld = exec_all().group(8, 0);
- src_reg left = component(tmp, 7);
- dst_reg right = horiz_offset(tmp, 8);
- set_condmod(mod, ubld.emit(opcode, right, left, right));
+ if (dispatch_width() > i * 4) {
+ left = component(tmp, i * 5 - 1);
+ right = horiz_offset(tmp, i * 5);
+ set_condmod(mod, ubld.emit(opcode, right, left, right));
+
+ left = component(tmp, i * 7 - 1);
+ right = horiz_offset(tmp, i * 7);
+ set_condmod(mod, ubld.emit(opcode, right, left, right));
+ }
}
}
ALU1(RNDE)
ALU1(RNDU)
ALU1(RNDZ)
+ ALU2(ROL)
+ ALU2(ROR)
ALU2(SAD2)
ALU2_ACC(SADA2)
ALU2(SEL)
emit(BRW_OPCODE_CSEL,
retype(dst, BRW_REGISTER_TYPE_F),
retype(src0, BRW_REGISTER_TYPE_F),
- retype(src1, BRW_REGISTER_TYPE_F),
- src2));
+ retype(fix_byte_src(src1), BRW_REGISTER_TYPE_F),
+ fix_byte_src(src2)));
}
/**
return inst;
}
+ instruction *
+ UNDEF(const dst_reg &dst) const
+ {
+ assert(dst.file == VGRF);
+ instruction *inst = emit(SHADER_OPCODE_UNDEF,
+ retype(dst, BRW_REGISTER_TYPE_UD));
+ inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE;
+
+ return inst;
+ }
+
backend_shader *shader;
+ /**
+ * Byte sized operands are not supported for src1 on Gen11+.
+ */
+ src_reg
+ fix_byte_src(const src_reg &src) const
+ {
+ if (shader->devinfo->gen < 11 || type_sz(src.type) != 1)
+ return src;
+
+ dst_reg temp = vgrf(src.type == BRW_REGISTER_TYPE_UB ?
+ BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D);
+ MOV(temp, src);
+ return src_reg(temp);
+ }
+
private:
/**
* Workaround for negation of UD registers. See comment in
src_reg
fix_3src_operand(const src_reg &src) const
{
- if (src.file == VGRF || src.file == UNIFORM || src.stride > 1) {
+ switch (src.file) {
+ case FIXED_GRF:
+ /* FINISHME: Could handle scalar region, other stride=1 regions */
+ if (src.vstride != BRW_VERTICAL_STRIDE_8 ||
+ src.width != BRW_WIDTH_8 ||
+ src.hstride != BRW_HORIZONTAL_STRIDE_1)
+ break;
+ /* fallthrough */
+ case ATTR:
+ case VGRF:
+ case UNIFORM:
+ case IMM:
return src;
- } else {
- dst_reg expanded = vgrf(src.type);
- MOV(expanded, src);
- return expanded;
+ default:
+ break;
}
+
+ dst_reg expanded = vgrf(src.type);
+ MOV(expanded, src);
+ return expanded;
}
/**
}
}
-
- /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
- *
- * "When source or destination datatype is 64b or operation is
- * integer DWord multiply, regioning in Align1 must follow
- * these rules:
- *
- * [...]
- *
- * 3. Source and Destination offset must be the same, except
- * the case of scalar source."
- *
- * This helper just detects when we're in this case.
- */
- bool
- need_matching_subreg_offset(enum opcode opcode,
- enum brw_reg_type type) const
- {
- if (!shader->devinfo->is_cherryview &&
- !gen_device_info_is_9lp(shader->devinfo))
- return false;
-
- if (type_sz(type) > 4)
- return true;
-
- if (opcode == BRW_OPCODE_MUL &&
- !brw_reg_type_is_floating_point(type))
- return true;
-
- return false;
- }
-
bblock_t *block;
exec_node *cursor;
projects / mesa.git / blobdiff