Added few more stubs so that control reaches to DestroyDevice().

[mesa.git] / src / intel / compiler / brw_fs_builder.h

diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index fef3dd01b5b91b57d166c5ca68797415d5699152..bdd106383894afbe060100f7e8e87e74acd55775 100644 (file)
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -140,7 +140,7 @@ namespace brw {
        * Alias for group() with width equal to eight.
        */
       fs_builder
-      half(unsigned i) const
+      quarter(unsigned i) const
       {
          return group(8, i);
       }
@@ -242,24 +242,6 @@ namespace brw {
          return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
       }
 
-      /**
-       * Get the mask of SIMD channels enabled by dispatch and not yet
-       * disabled by discard.
-       */
-      src_reg
-      sample_mask_reg() const
-      {
-         if (shader->stage != MESA_SHADER_FRAGMENT) {
-            return brw_imm_d(0xffffffff);
-         } else if (brw_wm_prog_data(shader->stage_prog_data)->uses_kill) {
-            return brw_flag_reg(0, 1);
-         } else {
-            assert(shader->devinfo->gen >= 6 && dispatch_width() <= 16);
-            return retype(brw_vec1_grf((_group >= 16 ? 2 : 1), 7),
-                          BRW_REGISTER_TYPE_UD);
-         }
-      }
-
       /**
        * Insert an instruction into the program.
        */
@@ -362,7 +344,16 @@ namespace brw {
       emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[],
            unsigned n) const
       {
-         return emit(instruction(opcode, dispatch_width(), dst, srcs, n));
+         /* Use the emit() methods for specific operand counts to ensure that
+          * opcode-specific operand fixups occur.
+          */
+         if (n == 2) {
+            return emit(opcode, dst, srcs[0], srcs[1]);
+         } else if (n == 3) {
+            return emit(opcode, dst, srcs[0], srcs[1], srcs[2]);
+         } else {
+            return emit(instruction(opcode, dispatch_width(), dst, srcs, n));
+         }
       }
 
       /**
@@ -424,7 +415,7 @@ namespace brw {
          const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
          const dst_reg dst = vgrf(src.type);
 
-         ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index)->flag_subreg = 2;
+         ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
          ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
 
          return src_reg(component(dst, 0));