* In the end, while base_offset is nice to look at in the generated
* code, using it saves us 0 instructions and would require quite a bit
* of case-by-case work. It's just not worth it.
+ *
+ * There's some sort of HW bug on Gen12 which causes issues if we write
+ * to the address register in control-flow. Since we only ever touch
+ * the address register from the generator, we can easily enough work
+ * around it by setting NoMask on the add.
*/
+ brw_push_insn_state(p);
+ if (devinfo->gen == 12)
+ brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
+ brw_pop_insn_state(p);
brw_set_default_swsb(p, tgl_swsb_regdist(1));
if (type_sz(reg.type) > 4 &&
((devinfo->gen == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
- !devinfo->has_64bit_types)) {
+ !devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
* 64-bit sources.
brw_inst_set_header_present(devinfo, insn, false);
brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
- brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
- /* Note that even though the thread has a URB resource associated with it,
- * we set the "do not dereference URB" bit, because the URB resource is
- * managed by the fixed-function unit, so it will free it automatically.
- */
- brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
+ if (devinfo->gen < 11) {
+ brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
+
+ /* Note that even though the thread has a URB resource associated with it,
+ * we set the "do not dereference URB" bit, because the URB resource is
+ * managed by the fixed-function unit, so it will free it automatically.
+ */
+ brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
+ }
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
{
brw_barrier(p, src);
- brw_set_default_swsb(p, tgl_swsb_null());
- brw_WAIT(p);
+ if (devinfo->gen >= 12) {
+ brw_set_default_swsb(p, tgl_swsb_null());
+ brw_SYNC(p, TGL_SYNC_BAR);
+ } else {
+ brw_WAIT(p);
+ }
}
bool
brw_set_default_group(p, inst->group + lower_size * i);
if (i > 0) {
- brw_set_default_swsb(p, tgl_swsb_null());
- brw_SYNC(p, TGL_SYNC_ALLRD);
+ assert(swsb.mode & TGL_SBID_SET);
+ brw_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid));
} else {
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
}
brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
- if (i + 1 < inst->exec_size / lower_size)
- brw_set_default_swsb(p, tgl_swsb_regdist(1));
- else
- brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
-
+ brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
block_size,
inst->offset + block_size * REG_SIZE * i);
this->dispatch_width = dispatch_width;
int start_offset = p->next_insn_offset;
+
+ /* `send_count` explicitly does not include spills or fills, as we'd
+ * like to use it as a metric for intentional memory access or other
+ * shared function use. Otherwise, subtle changes to scheduling or
+ * register allocation could cause it to fluctuate wildly - and that
+ * effect is already counted in spill/fill counts.
+ */
int spill_count = 0, fill_count = 0;
- int loop_count = 0;
+ int loop_count = 0, send_count = 0;
+ bool is_accum_used = false;
struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
last_insn_offset = p->next_insn_offset;
}
+ /* GEN:BUG:14010017096:
+ *
+ * Clear accumulator register before end of thread.
+ */
+ if (inst->eot && is_accum_used && devinfo->gen >= 12) {
+ brw_set_default_exec_size(p, BRW_EXECUTE_16);
+ brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+ brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
+ brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
+ last_insn_offset = p->next_insn_offset;
+ }
+
+ if (!is_accum_used && !inst->eot) {
+ is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
+ inst->dst.is_accumulator();
+ }
+
if (unlikely(debug_flag))
disasm_annotate(disasm_info, inst, p->next_insn_offset);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);
+ brw_set_default_swsb(p, inst->sched);
unsigned exec_size = inst->exec_size;
if (devinfo->gen == 7 && !devinfo->is_haswell &&
brw_math_function(inst->opcode),
inst->base_mrf, src[0],
BRW_MATH_PRECISION_FULL);
+ send_count++;
}
break;
case SHADER_OPCODE_INT_QUOTIENT:
gen4_math(p, dst, brw_math_function(inst->opcode),
inst->base_mrf, src[0],
BRW_MATH_PRECISION_FULL);
+ send_count++;
}
break;
case FS_OPCODE_LINTERP:
case SHADER_OPCODE_SEND:
generate_send(inst, dst, src[0], src[1], src[2],
inst->ex_mlen > 0 ? src[3] : brw_null_reg());
+ if ((inst->desc & 0xff) == BRW_BTI_STATELESS ||
+ (inst->desc & 0xff) == GEN8_BTI_STATELESS_NON_COHERENT) {
+ if (inst->size_written)
+ fill_count++;
+ else
+ spill_count++;
+ } else {
+ send_count++;
+ }
break;
case SHADER_OPCODE_GET_BUFFER_SIZE:
generate_get_buffer_size(inst, dst, src[0], src[1]);
+ send_count++;
break;
case SHADER_OPCODE_TEX:
case FS_OPCODE_TXB:
case SHADER_OPCODE_SAMPLEINFO:
assert(inst->src[0].file == BAD_FILE);
generate_tex(inst, dst, src[1], src[2]);
+ send_count++;
break;
case FS_OPCODE_DDX_COARSE:
case SHADER_OPCODE_URB_READ_SIMD8:
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
generate_urb_read(inst, dst, src[0]);
+ send_count++;
break;
case SHADER_OPCODE_URB_WRITE_SIMD8:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
generate_urb_write(inst, src[0]);
+ send_count++;
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
assert(inst->force_writemask_all);
generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
+ send_count++;
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
assert(inst->force_writemask_all);
generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
+ send_count++;
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
+ send_count++;
break;
case FS_OPCODE_REP_FB_WRITE:
case FS_OPCODE_FB_WRITE:
generate_fb_write(inst, src[0]);
+ send_count++;
break;
case FS_OPCODE_FB_READ:
generate_fb_read(inst, dst, src[0]);
+ send_count++;
break;
case FS_OPCODE_DISCARD_JUMP:
assert(src[1].file == BRW_IMMEDIATE_VALUE);
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, src[1].ud, src[2].ud);
+ send_count++;
+ break;
+
+ case FS_OPCODE_SCHEDULING_FENCE:
+ if (unlikely(debug_flag))
+ disasm_info->use_tail = true;
break;
case SHADER_OPCODE_INTERLOCK:
brw_find_live_channel(p, dst, mask);
break;
}
-
+ case FS_OPCODE_LOAD_LIVE_CHANNELS: {
+ assert(devinfo->gen >= 8);
+ assert(inst->force_writemask_all && inst->group == 0);
+ assert(inst->dst.file == BAD_FILE);
+ brw_set_default_exec_size(p, BRW_EXECUTE_1);
+ brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg),
+ BRW_REGISTER_TYPE_UD),
+ retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
+ break;
+ }
case SHADER_OPCODE_BROADCAST:
assert(inst->force_writemask_all);
brw_broadcast(p, dst, src[0], src[1]);
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
+ send_count++;
break;
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
+ send_count++;
break;
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
+ send_count++;
break;
case CS_OPCODE_CS_TERMINATE:
generate_cs_terminate(inst, src[0]);
+ send_count++;
break;
case SHADER_OPCODE_BARRIER:
generate_barrier(inst, src[0]);
+ send_count++;
break;
case BRW_OPCODE_DIM:
fprintf(stderr, "Native code for %s (sha1 %s)\n"
"SIMD%d shader: %d instructions. %d loops. %u cycles. "
- "%d:%d spills:fills. "
+ "%d:%d spills:fills, %u sends, "
"scheduled with mode %s. "
"Promoted %u constants. "
"Compacted %d to %d bytes (%.0f%%)\n",
shader_name, sha1buf,
dispatch_width, before_size / 16,
loop_count, cfg->cycle_count,
- spill_count, fill_count,
+ spill_count, fill_count, send_count,
shader_stats.scheduler_mode,
shader_stats.promoted_constants,
before_size, after_size,
compiler->shader_debug_log(log_data,
"%s SIMD%d shader: %d inst, %d loops, %u cycles, "
- "%d:%d spills:fills, "
+ "%d:%d spills:fills, %u sends, "
"scheduled with mode %s, "
"Promoted %u constants, "
"compacted %d to %d bytes.",
_mesa_shader_stage_to_abbrev(stage),
dispatch_width, before_size / 16,
loop_count, cfg->cycle_count,
- spill_count, fill_count,
+ spill_count, fill_count, send_count,
shader_stats.scheduler_mode,
shader_stats.promoted_constants,
before_size, after_size);
projects / mesa.git / blobdiff