#include "brw_eu.h"
#include "brw_fs.h"
#include "brw_cfg.h"
+#include "util/mesa-sha1.h"
static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
const unsigned phys_width = compressed ? inst->exec_size / 2 :
inst->exec_size;
+ const unsigned max_hw_width = 16;
+
/* XXX - The equation above is strictly speaking not correct on
* hardware that supports unbalanced GRF writes -- On Gen9+
* each decompressed chunk of the instruction may have a
brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, reg->stride, 1, 0);
} else {
- const unsigned width = MIN2(reg_width, phys_width);
+ const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}
fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
struct brw_stage_prog_data *prog_data,
- unsigned promoted_constants,
+ struct shader_stats shader_stats,
bool runtime_check_aads_emit,
gl_shader_stage stage)
: compiler(compiler), log_data(log_data),
devinfo(compiler->devinfo),
prog_data(prog_data),
- promoted_constants(promoted_constants),
+ shader_stats(shader_stats),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
stage(stage), mem_ctx(mem_ctx)
{
desc, desc_imm, ex_desc, ex_desc_imm,
inst->eot);
if (inst->check_tdr)
- brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDSC);
+ brw_inst_set_opcode(p->devinfo, brw_last_inst,
+ devinfo->gen >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
} else {
brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
inst->eot);
struct brw_reg implied_header,
GLuint nr)
{
- uint32_t msg_control;
-
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
if (devinfo->gen < 6) {
brw_pop_insn_state(p);
}
- if (inst->opcode == FS_OPCODE_REP_FB_WRITE) {
- assert(inst->group == 0 && inst->exec_size == 16);
- msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
-
- } else if (prog_data->dual_src_blend) {
- assert(inst->exec_size == 8);
-
- if (inst->group % 16 == 0)
- msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
- else if (inst->group % 16 == 8)
- msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
- else
- unreachable("Invalid dual-source FB write instruction group");
-
- } else {
- assert(inst->group == 0 || (inst->group == 16 && inst->exec_size == 16));
-
- if (inst->exec_size == 16)
- msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
- else if (inst->exec_size == 8)
- msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
- else
- unreachable("Invalid FB write execution size");
- }
+ uint32_t msg_control = brw_fb_write_msg_control(inst, prog_data);
/* We assume render targets start at 0, because headerless FB write
* messages set "Render Target Index" to 0. Using a different binding
struct brw_reg gdst = suboffset(dst, group);
struct brw_reg dst_d = retype(spread(gdst, 2),
BRW_REGISTER_TYPE_D);
+ assert(dst.hstride == 1);
brw_MOV(p, dst_d,
retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
brw_MOV(p, byte_offset(dst_d, 4),
retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
} else {
- brw_MOV(p, suboffset(dst, group),
+ brw_MOV(p, suboffset(dst, group * dst.hstride),
retype(brw_VxH_indirect(0, 0), src.type));
}
}
4 * inst->dst.stride, 1, 4 * inst->dst.stride),
stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
- brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
- brw_inst_set_no_dd_check(devinfo, insn, c > 0);
+ if (devinfo->gen < 12) {
+ brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
+ brw_inst_set_no_dd_check(devinfo, insn, c > 0);
+ }
}
break;
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, header);
- brw_set_src1(p, send, brw_imm_ud(0u));
+ if (devinfo->gen < 12)
+ brw_set_src1(p, send, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
brw_set_dest(p, insn, brw_null_reg());
brw_set_src0(p, insn, payload);
- brw_set_src1(p, insn, brw_imm_ud(0u));
+ if (devinfo->gen < 12)
+ brw_set_src1(p, insn, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
- brw_set_src1(p, insn, brw_imm_ud(0u));
+ if (devinfo->gen < 12)
+ brw_set_src1(p, insn, brw_imm_ud(0u));
/* Terminate a compute shader by sending a message to the thread spawner.
*/
*/
struct brw_reg delta_x = src[0];
struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
- struct brw_reg interp = stride(src[1], 0, 1, 0);
+ struct brw_reg interp = src[1];
brw_inst *i[2];
- /* fs_visitor::lower_linterp() will do the lowering to MAD instructions for
+ /* nir_lower_interpolation() will do the lowering to MAD instructions for
* us on gen11+
*/
assert(devinfo->gen < 11);
{
unsigned vstride, width;
- if (inst->opcode == FS_OPCODE_DDX_FINE) {
- /* produce accurate derivatives */
- vstride = BRW_VERTICAL_STRIDE_2;
- width = BRW_WIDTH_2;
- } else {
- /* replicate the derivative at the top-left pixel to other pixels */
- vstride = BRW_VERTICAL_STRIDE_4;
- width = BRW_WIDTH_4;
- }
+ if (devinfo->gen >= 8) {
+ if (inst->opcode == FS_OPCODE_DDX_FINE) {
+ /* produce accurate derivatives */
+ vstride = BRW_VERTICAL_STRIDE_2;
+ width = BRW_WIDTH_2;
+ } else {
+ /* replicate the derivative at the top-left pixel to other pixels */
+ vstride = BRW_VERTICAL_STRIDE_4;
+ width = BRW_WIDTH_4;
+ }
+
+ struct brw_reg src0 = byte_offset(src, type_sz(src.type));;
+ struct brw_reg src1 = src;
- struct brw_reg src0 = byte_offset(src, type_sz(src.type));;
- struct brw_reg src1 = src;
+ src0.vstride = vstride;
+ src0.width = width;
+ src0.hstride = BRW_HORIZONTAL_STRIDE_0;
+ src1.vstride = vstride;
+ src1.width = width;
+ src1.hstride = BRW_HORIZONTAL_STRIDE_0;
- src0.vstride = vstride;
- src0.width = width;
- src0.hstride = BRW_HORIZONTAL_STRIDE_0;
- src1.vstride = vstride;
- src1.width = width;
- src1.hstride = BRW_HORIZONTAL_STRIDE_0;
+ brw_ADD(p, dst, src0, negate(src1));
+ } else {
+ /* On Haswell and earlier, the region used above appears to not work
+ * correctly for compressed instructions. At least on Haswell and
+ * Iron Lake, compressed ALIGN16 instructions do work. Since we
+ * would have to split to SIMD8 no matter which method we choose, we
+ * may as well use ALIGN16 on all platforms gen7 and earlier.
+ */
+ struct brw_reg src0 = stride(src, 4, 4, 1);
+ struct brw_reg src1 = stride(src, 4, 4, 1);
+ if (inst->opcode == FS_OPCODE_DDX_FINE) {
+ src0.swizzle = BRW_SWIZZLE_XXZZ;
+ src1.swizzle = BRW_SWIZZLE_YYWW;
+ } else {
+ src0.swizzle = BRW_SWIZZLE_XXXX;
+ src1.swizzle = BRW_SWIZZLE_YYYY;
+ }
- brw_ADD(p, dst, src0, negate(src1));
+ brw_push_insn_state(p);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
+ brw_ADD(p, dst, negate(src0), src1);
+ brw_pop_insn_state(p);
+ }
}
/* The negate_value boolean is used to negate the derivative computation for
}
} else {
/* replicate the derivative at the top-left pixel to other pixels */
- struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
- struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
+ if (devinfo->gen >= 8) {
+ struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
+ struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
- brw_ADD(p, dst, negate(src0), src1);
+ brw_ADD(p, dst, negate(src0), src1);
+ } else {
+ /* On Haswell and earlier, the region used above appears to not work
+ * correctly for compressed instructions. At least on Haswell and
+ * Iron Lake, compressed ALIGN16 instructions do work. Since we
+ * would have to split to SIMD8 no matter which method we choose, we
+ * may as well use ALIGN16 on all platforms gen7 and earlier.
+ */
+ struct brw_reg src0 = stride(src, 4, 4, 1);
+ struct brw_reg src1 = stride(src, 4, 4, 1);
+ src0.swizzle = BRW_SWIZZLE_XXXX;
+ src1.swizzle = BRW_SWIZZLE_ZZZZ;
+
+ brw_push_insn_state(p);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
+ brw_ADD(p, dst, negate(src0), src1);
+ brw_pop_insn_state(p);
+ }
}
}
}
int
-fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
+fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
+ struct brw_compile_stats *stats)
{
/* align to 64 byte boundary. */
while (p->next_insn_offset % 64)
case SHADER_OPCODE_MEMORY_FENCE:
assert(src[1].file == BRW_IMMEDIATE_VALUE);
- brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, src[1].ud);
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, src[1].ud, src[2].ud);
break;
case SHADER_OPCODE_INTERLOCK:
assert(devinfo->gen >= 9);
/* The interlock is basically a memory fence issued via sendc */
- brw_memory_fence(p, dst, src[0], BRW_OPCODE_SENDC, false);
+ brw_memory_fence(p, dst, src[0], BRW_OPCODE_SENDC, false, /* bti */ 0);
break;
case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
break;
case SHADER_OPCODE_CLUSTER_BROADCAST: {
- assert(src[0].type == dst.type);
assert(!src[0].negate && !src[0].abs);
assert(src[1].file == BRW_IMMEDIATE_VALUE);
assert(src[1].type == BRW_REGISTER_TYPE_UD);
assert(src[2].type == BRW_REGISTER_TYPE_UD);
const unsigned component = src[1].ud;
const unsigned cluster_size = src[2].ud;
+ unsigned vstride = cluster_size;
+ unsigned width = cluster_size;
+
+ /* The maximum exec_size is 32, but the maximum width is only 16. */
+ if (inst->exec_size == width) {
+ vstride = 0;
+ width = 1;
+ }
+
struct brw_reg strided = stride(suboffset(src[0], component),
- cluster_size, cluster_size, 0);
+ vstride, width, 0);
if (type_sz(src[0].type) > 4 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
/* IVB has an issue (which we found empirically) where it reads
* indirect here to handle adding 4 bytes to the offset and avoid
* the extra ADD to the register file.
*/
+ assert(src[0].type == dst.type);
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
subscript(strided, BRW_REGISTER_TYPE_D, 0));
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
break;
- case SHADER_OPCODE_RND_MODE:
+ case SHADER_OPCODE_RND_MODE: {
+ assert(src[0].file == BRW_IMMEDIATE_VALUE);
+ /*
+ * Changes the floating point rounding mode updating the control
+ * register field defined at cr0.0[5-6] bits.
+ */
+ enum brw_rnd_mode mode =
+ (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
+ brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
+ }
+ break;
+
+ case SHADER_OPCODE_FLOAT_CONTROL_MODE:
assert(src[0].file == BRW_IMMEDIATE_VALUE);
- brw_rounding_mode(p, (brw_rnd_mode) src[0].d);
+ assert(src[1].file == BRW_IMMEDIATE_VALUE);
+ brw_float_controls_mode(p, src[0].d, src[1].d);
break;
default:
if (inst->conditional_mod)
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
- brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
- brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
+ if (devinfo->gen < 12) {
+ brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
+ brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
+ }
}
}
int after_size = p->next_insn_offset - start_offset;
if (unlikely(debug_flag)) {
- fprintf(stderr, "Native code for %s\n"
- "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
- " bytes (%.0f%%)\n",
- shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
- spill_count, fill_count, promoted_constants, before_size, after_size,
+ unsigned char sha1[21];
+ char sha1buf[41];
+
+ _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst),
+ after_size, sha1);
+ _mesa_sha1_format(sha1buf, sha1);
+
+ fprintf(stderr, "Native code for %s (sha1 %s)\n"
+ "SIMD%d shader: %d instructions. %d loops. %u cycles. "
+ "%d:%d spills:fills. "
+ "scheduled with mode %s. "
+ "Promoted %u constants. "
+ "Compacted %d to %d bytes (%.0f%%)\n",
+ shader_name, sha1buf,
+ dispatch_width, before_size / 16,
+ loop_count, cfg->cycle_count,
+ spill_count, fill_count,
+ shader_stats.scheduler_mode,
+ shader_stats.promoted_constants,
+ before_size, after_size,
100.0f * (before_size - after_size) / before_size);
- dump_assembly(p->store, disasm_info);
+ /* overriding the shader makes disasm_info invalid */
+ if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
+ dump_assembly(p->store, disasm_info);
+ } else {
+ fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
+ }
}
ralloc_free(disasm_info);
assert(validated);
compiler->shader_debug_log(log_data,
"%s SIMD%d shader: %d inst, %d loops, %u cycles, "
- "%d:%d spills:fills, Promoted %u constants, "
+ "%d:%d spills:fills, "
+ "scheduled with mode %s, "
+ "Promoted %u constants, "
"compacted %d to %d bytes.",
_mesa_shader_stage_to_abbrev(stage),
dispatch_width, before_size / 16,
- loop_count, cfg->cycle_count, spill_count,
- fill_count, promoted_constants, before_size,
- after_size);
+ loop_count, cfg->cycle_count,
+ spill_count, fill_count,
+ shader_stats.scheduler_mode,
+ shader_stats.promoted_constants,
+ before_size, after_size);
+ if (stats) {
+ stats->dispatch_width = dispatch_width;
+ stats->instructions = before_size / 16;
+ stats->loops = loop_count;
+ stats->cycles = cfg->cycle_count;
+ stats->spills = spill_count;
+ stats->fills = fill_count;
+ }
return start_offset;
}
projects / mesa.git / blobdiff