}
case nir_intrinsic_load_num_work_groups: {
+ assert(nir_dest_bit_size(instr->dest) == 32);
const unsigned surface =
cs_prog_data->binding_table.work_groups_start;
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(surface);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
- srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); /* num components */
-
- /* Read the 3 GLuint components of gl_NumWorkGroups */
- for (unsigned i = 0; i < 3; i++) {
- srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(i << 2);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(3); /* num components */
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(0);
+ fs_inst *inst =
bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
- offset(dest, bld, i), srcs, SURFACE_LOGICAL_NUM_SRCS);
- }
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = 3 * dispatch_width * 4;
break;
}
bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(1));
break;
+ case nir_intrinsic_load_reloc_const_intel: {
+ uint32_t id = nir_intrinsic_param_idx(instr);
+ bld.emit(SHADER_OPCODE_MOV_RELOC_IMM,
+ dest, brw_imm_ud(id));
+ break;
+ }
+
case nir_intrinsic_load_uniform: {
/* Offsets are in bytes but they should always aligned to
* the type size