/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
- const fs_reg &texture)
+ const fs_reg &texture,
+ const fs_reg &texture_handle)
{
const fs_reg dest = vgrf(glsl_type::uvec4_type);
fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
srcs[TEX_LOGICAL_SRC_SURFACE] = texture;
- srcs[TEX_LOGICAL_SRC_SAMPLER] = texture;
+ srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0);
+ srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = texture_handle;
srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components);
srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
stage_prog_data->curb_read_length = 0;
stage_prog_data->dispatch_grf_start_reg = 2;
wm_prog_data->dispatch_grf_start_reg_16 = 2;
+ wm_prog_data->dispatch_grf_start_reg_32 = 2;
grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */
calculate_cfg();
*/
this->wpos_w = vgrf(glsl_type::float_type);
abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
- component(interp_reg(VARYING_SLOT_POS, 3), 0));
+ interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = vgrf(glsl_type::float_type);
abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
void
fs_visitor::emit_interpolation_setup_gen6()
{
- struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
-
fs_builder abld = bld.annotate("compute pixel centers");
- if (devinfo->gen >= 8 || dispatch_width == 8) {
- /* The "Register Region Restrictions" page says for BDW (and newer,
- * presumably):
- *
- * "When destination spans two registers, the source may be one or
- * two registers. The destination elements must be evenly split
- * between the two registers."
- *
- * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
- * compute our pixel centers.
- */
- fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8),
- BRW_REGISTER_TYPE_UW);
-
- const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0);
- dbld.ADD(int_pixel_xy,
- fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
- fs_reg(brw_imm_v(0x11001010)));
-
- this->pixel_x = vgrf(glsl_type::float_type);
- this->pixel_y = vgrf(glsl_type::float_type);
- abld.emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy);
- abld.emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy);
- } else {
- /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
- *
- * "When destination spans two registers, the source MUST span two
- * registers."
- *
- * Since the GRF source of the ADD will only read a single register, we
- * must do two separate ADDs in SIMD16.
- */
- fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
- fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
- int_pixel_x.type = BRW_REGISTER_TYPE_UW;
- int_pixel_y.type = BRW_REGISTER_TYPE_UW;
- abld.ADD(int_pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010)));
- abld.ADD(int_pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100)));
-
- /* As of gen6, we can no longer mix float and int sources. We have
- * to turn the integer pixel centers into floats for their actual
- * use.
- */
- this->pixel_x = vgrf(glsl_type::float_type);
- this->pixel_y = vgrf(glsl_type::float_type);
- abld.MOV(this->pixel_x, int_pixel_x);
- abld.MOV(this->pixel_y, int_pixel_y);
+
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+
+ for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
+ const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
+ struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW);
+
+ if (devinfo->gen >= 8 || dispatch_width == 8) {
+ /* The "Register Region Restrictions" page says for BDW (and newer,
+ * presumably):
+ *
+ * "When destination spans two registers, the source may be one or
+ * two registers. The destination elements must be evenly split
+ * between the two registers."
+ *
+ * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
+ * to compute our pixel centers.
+ */
+ const fs_builder dbld =
+ abld.exec_all().group(hbld.dispatch_width() * 2, 0);
+ fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
+
+ dbld.ADD(int_pixel_xy,
+ fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)),
+ fs_reg(brw_imm_v(0x11001010)));
+
+ hbld.emit(FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy);
+ hbld.emit(FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy);
+ } else {
+ /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
+ *
+ * "When destination spans two registers, the source MUST span
+ * two registers."
+ *
+ * Since the GRF source of the ADD will only read a single register,
+ * we must do two separate ADDs in SIMD16.
+ */
+ const fs_reg int_pixel_x = hbld.vgrf(BRW_REGISTER_TYPE_UW);
+ const fs_reg int_pixel_y = hbld.vgrf(BRW_REGISTER_TYPE_UW);
+
+ hbld.ADD(int_pixel_x,
+ fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010)));
+ hbld.ADD(int_pixel_y,
+ fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100)));
+
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ hbld.MOV(offset(pixel_x, hbld, i), int_pixel_x);
+ hbld.MOV(offset(pixel_y, hbld, i), int_pixel_y);
+ }
}
abld = bld.annotate("compute pos.w");
* pixels are lit. Then, for each channel that is unlit,
* replace the centroid data with non-centroid data.
*/
- bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
+ for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
+ bld.exec_all().group(1, 0)
+ .MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW),
+ retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW));
+ }
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
if (!(centroid_modes & (1 << i)))
return write;
}
+void
+fs_visitor::emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha)
+{
+ /* We need to compute alpha to coverage dithering manually in shader
+ * and replace sample mask store with the bitwise-AND of sample mask and
+ * alpha to coverage dithering.
+ *
+ * The following formula is used to compute final sample mask:
+ * m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
+ * dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
+ * 0x0808 * (m & 2) | 0x0100 * (m & 1)
+ * sample_mask = sample_mask & dither_mask
+ *
+ * It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
+ * least significant bits of the result:
+ * 0.0000 0000000000000000
+ * 0.0625 0000000100000000
+ * 0.1250 0001000000010000
+ * 0.1875 0001000100010000
+ * 0.2500 1000100010001000
+ * 0.3125 1000100110001000
+ * 0.3750 1001100010011000
+ * 0.4375 1001100110011000
+ * 0.5000 1010101010101010
+ * 0.5625 1010101110101010
+ * 0.6250 1011101010111010
+ * 0.6875 1011101110111010
+ * 0.7500 1110111011101110
+ * 0.8125 1110111111101110
+ * 0.8750 1111111011111110
+ * 0.9375 1111111111111110
+ * 1.0000 1111111111111111
+ */
+ const fs_builder abld = bld.annotate("compute alpha_to_coverage & "
+ "sample_mask");
+
+ /* clamp(src0_alpha, 0.f, 1.f) */
+ const fs_reg float_tmp = abld.vgrf(BRW_REGISTER_TYPE_F);
+ set_saturate(true, abld.MOV(float_tmp, src0_alpha));
+
+ /* 16.0 * clamp(src0_alpha, 0.0, 1.0) */
+ abld.MUL(float_tmp, float_tmp, brw_imm_f(16.0));
+
+ /* m = int(16.0 * clamp(src0_alpha, 0.0, 1.0)) */
+ const fs_reg m = abld.vgrf(BRW_REGISTER_TYPE_UW);
+ abld.MOV(m, float_tmp);
+
+ /* 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) */
+ const fs_reg int_tmp_1 = abld.vgrf(BRW_REGISTER_TYPE_UW);
+ const fs_reg shift_const = abld.vgrf(BRW_REGISTER_TYPE_UD);
+ abld.MOV(shift_const, brw_imm_d(0xfea80));
+ abld.AND(int_tmp_1, m, brw_imm_uw(~3));
+ abld.SHR(int_tmp_1, shift_const, int_tmp_1);
+ abld.AND(int_tmp_1, int_tmp_1, brw_imm_uw(0xf));
+ abld.MUL(int_tmp_1, int_tmp_1, brw_imm_uw(0x1111));
+
+ /* 0x0808 * (m & 2) */
+ const fs_reg int_tmp_2 = abld.vgrf(BRW_REGISTER_TYPE_UW);
+ abld.AND(int_tmp_2, m, brw_imm_uw(2));
+ abld.MUL(int_tmp_2, int_tmp_2, brw_imm_uw(0x0808));
+
+ abld.OR(int_tmp_1, int_tmp_1, int_tmp_2);
+
+ /* 0x0100 * (m & 1) */
+ const fs_reg int_tmp_3 = abld.vgrf(BRW_REGISTER_TYPE_UW);
+ abld.AND(int_tmp_3, m, brw_imm_uw(1));
+ abld.MUL(int_tmp_3, int_tmp_3, brw_imm_uw(0x0100));
+
+ abld.OR(int_tmp_1, int_tmp_1, int_tmp_3);
+
+ /* sample_mask = sample_mask & dither_mask */
+ const fs_reg mask = abld.vgrf(BRW_REGISTER_TYPE_UD);
+ abld.AND(mask, sample_mask, int_tmp_1);
+ sample_mask = mask;
+}
+
void
fs_visitor::emit_fb_writes()
{
"in SIMD16+ mode.\n");
}
+ /* ANV doesn't know about sample mask output during the wm key creation
+ * so we compute if we need replicate alpha and emit alpha to coverage
+ * workaround here.
+ */
+ prog_data->replicate_alpha = key->alpha_test_replicate_alpha ||
+ (key->nr_color_regions > 1 && key->alpha_to_coverage &&
+ (sample_mask.file == BAD_FILE || devinfo->gen == 6));
+
+ /* From the SKL PRM, Volume 7, "Alpha Coverage":
+ * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
+ * hardware, regardless of the state setting for this feature."
+ */
+ if (devinfo->gen > 6 && key->alpha_to_coverage &&
+ sample_mask.file != BAD_FILE && this->outputs[0].file != BAD_FILE)
+ emit_alpha_to_coverage_workaround(offset(this->outputs[0], bld, 3));
+
for (int target = 0; target < key->nr_color_regions; target++) {
/* Skip over outputs that weren't written. */
if (this->outputs[target].file == BAD_FILE)
ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
fs_reg src0_alpha;
- if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
+ if (devinfo->gen >= 6 && prog_data->replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], bld, 3);
inst = emit_single_fb_write(abld, this->outputs[target],
per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
gs_vertex_count.ud);
} else {
- per_slot_offsets = vgrf(glsl_type::int_type);
+ per_slot_offsets = vgrf(glsl_type::uint_type);
bld.MUL(per_slot_offsets, gs_vertex_count,
brw_imm_ud(output_vertex_size_owords));
}
header_size);
fs_inst *inst = abld.emit(opcode, reg_undef, payload);
- inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
+
+ /* For ICL WA 1805992985 one needs additional write in the end. */
+ if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL)
+ inst->eot = false;
+ else
+ inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
+
inst->mlen = length + header_size;
inst->offset = urb_offset;
urb_offset = starting_urb_offset + slot + 1;
inst->mlen = 2;
inst->offset = 1;
return;
+ }
+
+ /* ICL WA 1805992985:
+ *
+ * ICLLP GPU hangs on one of tessellation vkcts tests with DS not done. The
+ * send cycle, which is a urb write with an eot must be 4 phases long and
+ * all 8 lanes must valid.
+ */
+ if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL) {
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(6), BRW_REGISTER_TYPE_UD);
+
+ /* Workaround requires all 8 channels (lanes) to be valid. This is
+ * understood to mean they all need to be alive. First trick is to find
+ * a live channel and copy its urb handle for all the other channels to
+ * make sure all handles are valid.
+ */
+ bld.exec_all().MOV(payload, bld.emit_uniformize(urb_handle));
+
+ /* Second trick is to use masked URB write where one can tell the HW to
+ * actually write data only for selected channels even though all are
+ * active.
+ * Third trick is to take advantage of the must-be-zero (MBZ) area in
+ * the very beginning of the URB.
+ *
+ * One masks data to be written only for the first channel and uses
+ * offset zero explicitly to land data to the MBZ area avoiding trashing
+ * any other part of the URB.
+ *
+ * Since the WA says that the write needs to be 4 phases long one uses
+ * 4 slots data. All are explicitly zeros in order to to keep the MBZ
+ * area written as zeros.
+ */
+ bld.exec_all().MOV(offset(payload, bld, 1), brw_imm_ud(0x10000u));
+ bld.exec_all().MOV(offset(payload, bld, 2), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 3), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 4), brw_imm_ud(0u));
+ bld.exec_all().MOV(offset(payload, bld, 5), brw_imm_ud(0u));
+
+ fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
+ reg_undef, payload);
+ inst->eot = true;
+ inst->mlen = 6;
+ inst->offset = 0;
}
}
void
fs_visitor::emit_barrier()
{
- assert(devinfo->gen >= 7);
- const uint32_t barrier_id_mask =
- devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;
+ uint32_t barrier_id_mask;
+ switch (devinfo->gen) {
+ case 7:
+ case 8:
+ barrier_id_mask = 0x0f000000u; break;
+ case 9:
+ case 10:
+ barrier_id_mask = 0x8f000000u; break;
+ case 11:
+ barrier_id_mask = 0x7f000000u; break;
+ default:
+ unreachable("barrier is only available on gen >= 7");
+ }
/* We are getting the barrier ID from the compute shader header */
assert(stage == MESA_SHADER_COMPUTE);
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
- const void *key,
+ const brw_base_prog_key *key,
struct brw_stage_prog_data *prog_data,
struct gl_program *prog,
const nir_shader *shader,
int shader_time_index)
: backend_shader(compiler, log_data, mem_ctx, shader,
&prog_data->base.base),
- key(&c->key), gs_compile(c),
+ key(&c->key.base), gs_compile(c),
prog_data(&prog_data->base.base), prog(NULL),
dispatch_width(8),
shader_time_index(shader_time_index),
void
fs_visitor::init()
{
- switch (stage) {
- case MESA_SHADER_FRAGMENT:
- key_tex = &((const brw_wm_prog_key *) key)->tex;
- break;
- case MESA_SHADER_VERTEX:
- key_tex = &((const brw_vs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_TESS_CTRL:
- key_tex = &((const brw_tcs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_TESS_EVAL:
- key_tex = &((const brw_tes_prog_key *) key)->tex;
- break;
- case MESA_SHADER_GEOMETRY:
- key_tex = &((const brw_gs_prog_key *) key)->tex;
- break;
- case MESA_SHADER_COMPUTE:
- key_tex = &((const brw_cs_prog_key*) key)->tex;
- break;
- default:
- unreachable("unhandled shader stage");
- }
+ this->key_tex = &key->tex;
this->max_dispatch_width = 32;
this->prog_data = this->stage_prog_data;
projects / mesa.git / blobdiff