#include <stdint.h>
#include "brw_eu_defines.h"
-#include "common/gen_device_info.h"
+#include "brw_reg_type.h"
+#include "dev/gen_device_info.h"
#ifdef __cplusplus
extern "C" {
} else { \
high = hi4; low = lo4; \
} \
- assert(((int) high) != -1 && ((int) low) != -1); \
+ assert(((int) high) != -1 && ((int) low) != -1);
/* A general macro for cases where the field has moved to several different
* bit locations across generations. GCC appears to combine cases where the
F(src1_da1_subreg_nr, 100, 96)
F(src1_da16_swiz_y, 99, 98)
F(src1_da16_swiz_x, 97, 96)
-F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
+F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
F(src0_vstride, 88, 85)
F(src0_width, 84, 82)
F(dst_da16_subreg_nr, 52, 52)
F(dst_da1_subreg_nr, 52, 48)
F(da16_writemask, 51, 48) /* Dst.ChanEn */
-F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
+F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
-F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
+F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
FF(flag_reg_nr,
* Three-source instructions:
* @{
*/
-F(3src_src2_reg_nr, 125, 118)
-F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
-F(3src_src2_swizzle, 114, 107)
-F(3src_src2_rep_ctrl, 106, 106)
-F(3src_src1_reg_nr, 104, 97)
-F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
-F(3src_src1_swizzle, 93, 86)
-F(3src_src1_rep_ctrl, 85, 85)
-F(3src_src0_reg_nr, 83, 76)
-F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
-F(3src_src0_swizzle, 72, 65)
-F(3src_src0_rep_ctrl, 64, 64)
-F(3src_dst_reg_nr, 63, 56)
-F(3src_dst_subreg_nr, 55, 53)
-F(3src_dst_writemask, 52, 49)
-F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
-F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
-F8(3src_src_type, 43, 42, 45, 43)
-F8(3src_src2_negate, 41, 41, 42, 42)
-F8(3src_src2_abs, 40, 40, 41, 41)
-F8(3src_src1_negate, 39, 39, 40, 40)
-F8(3src_src1_abs, 38, 38, 39, 39)
-F8(3src_src0_negate, 37, 37, 38, 38)
-F8(3src_src0_abs, 36, 36, 37, 37)
-F8(3src_flag_reg_nr, 34, 34, 33, 33)
-F8(3src_flag_subreg_nr, 33, 33, 32, 32)
-FF(3src_dst_reg_file,
+F(3src_src2_reg_nr, 125, 118) /* same in align1 */
+F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
+F(3src_a16_src2_swizzle, 114, 107)
+F(3src_a16_src2_rep_ctrl, 106, 106)
+F(3src_src1_reg_nr, 104, 97) /* same in align1 */
+F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
+F(3src_a16_src1_swizzle, 93, 86)
+F(3src_a16_src1_rep_ctrl, 85, 85)
+F(3src_src0_reg_nr, 83, 76) /* same in align1 */
+F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
+F(3src_a16_src0_swizzle, 72, 65)
+F(3src_a16_src0_rep_ctrl, 64, 64)
+F(3src_dst_reg_nr, 63, 56) /* same in align1 */
+F(3src_a16_dst_subreg_nr, 55, 53)
+F(3src_a16_dst_writemask, 52, 49)
+F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
+F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */
+F8(3src_a16_src_hw_type, 43, 42, 45, 43)
+F8(3src_src2_negate, 41, 41, 42, 42)
+F8(3src_src2_abs, 40, 40, 41, 41)
+F8(3src_src1_negate, 39, 39, 40, 40)
+F8(3src_src1_abs, 38, 38, 39, 39)
+F8(3src_src0_negate, 37, 37, 38, 38)
+F8(3src_src0_abs, 36, 36, 37, 37)
+F8(3src_a16_src1_type, -1, -1, 36, 36)
+F8(3src_a16_src2_type, -1, -1, 35, 35)
+F8(3src_a16_flag_reg_nr, 34, 34, 33, 33)
+F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32)
+FF(3src_a16_dst_reg_file,
/* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
/* 6: */ 32, 32,
/* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
F(3src_opcode, 6, 0)
/** @} */
+#define REG_TYPE(reg) \
+static inline void \
+brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
+ brw_inst *inst, enum brw_reg_type type) \
+{ \
+ unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
+ brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
+} \
+ \
+static inline enum brw_reg_type \
+brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
+ const brw_inst *inst) \
+{ \
+ unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
+ return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
+}
+
+REG_TYPE(dst)
+REG_TYPE(src)
+#undef REG_TYPE
+
+/**
+ * Three-source align1 instructions:
+ * @{
+ */
+/* Reserved 127:126 */
+/* src2_reg_nr same in align16 */
+FC(3src_a1_src2_subreg_nr, 117, 113, devinfo->gen >= 10)
+FC(3src_a1_src2_hstride, 112, 111, devinfo->gen >= 10)
+/* Reserved 110:109. src2 vstride is an implied parameter */
+FC(3src_a1_src2_hw_type, 108, 106, devinfo->gen >= 10)
+/* Reserved 105 */
+/* src1_reg_nr same in align16 */
+FC(3src_a1_src1_subreg_nr, 96, 92, devinfo->gen >= 10)
+FC(3src_a1_src1_hstride, 91, 90, devinfo->gen >= 10)
+FC(3src_a1_src1_vstride, 89, 88, devinfo->gen >= 10)
+FC(3src_a1_src1_hw_type, 87, 85, devinfo->gen >= 10)
+/* Reserved 84 */
+/* src0_reg_nr same in align16 */
+FC(3src_a1_src0_subreg_nr, 75, 71, devinfo->gen >= 10)
+FC(3src_a1_src0_hstride, 70, 69, devinfo->gen >= 10)
+FC(3src_a1_src0_vstride, 68, 67, devinfo->gen >= 10)
+FC(3src_a1_src0_hw_type, 66, 64, devinfo->gen >= 10)
+/* dst_reg_nr same in align16 */
+FC(3src_a1_dst_subreg_nr, 55, 54, devinfo->gen >= 10)
+FC(3src_a1_special_acc, 55, 52, devinfo->gen >= 10) /* aliases dst_subreg_nr */
+/* Reserved 51:50 */
+FC(3src_a1_dst_hstride, 49, 49, devinfo->gen >= 10)
+FC(3src_a1_dst_hw_type, 48, 46, devinfo->gen >= 10)
+FC(3src_a1_src2_reg_file, 45, 45, devinfo->gen >= 10)
+FC(3src_a1_src1_reg_file, 44, 44, devinfo->gen >= 10)
+FC(3src_a1_src0_reg_file, 43, 43, devinfo->gen >= 10)
+/* Source Modifier fields same in align16 */
+FC(3src_a1_dst_reg_file, 36, 36, devinfo->gen >= 10)
+FC(3src_a1_exec_type, 35, 35, devinfo->gen >= 10)
+/* Fields below this same in align16 */
+/** @} */
+
+#define REG_TYPE(reg) \
+static inline void \
+brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
+ brw_inst *inst, enum brw_reg_type type) \
+{ \
+ UNUSED enum gen10_align1_3src_exec_type exec_type = \
+ (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
+ inst); \
+ if (brw_reg_type_is_floating_point(type)) { \
+ assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
+ } else { \
+ assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
+ } \
+ unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
+ brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
+} \
+ \
+static inline enum brw_reg_type \
+brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
+ const brw_inst *inst) \
+{ \
+ enum gen10_align1_3src_exec_type exec_type = \
+ (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
+ inst); \
+ unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
+ return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
+}
+
+REG_TYPE(dst)
+REG_TYPE(src0)
+REG_TYPE(src1)
+REG_TYPE(src2)
+#undef REG_TYPE
+
+/**
+ * Three-source align1 instruction immediates:
+ * @{
+ */
+static inline uint16_t
+brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
+ const brw_inst *insn)
+{
+ assert(devinfo->gen >= 10);
+ return brw_inst_bits(insn, 82, 67);
+}
+
+static inline uint16_t
+brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
+ const brw_inst *insn)
+{
+ assert(devinfo->gen >= 10);
+ return brw_inst_bits(insn, 124, 109);
+}
+
+static inline void
+brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
+ brw_inst *insn, uint16_t value)
+{
+ assert(devinfo->gen >= 10);
+ brw_inst_set_bits(insn, 82, 67, value);
+}
+
+static inline void
+brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
+ brw_inst *insn, uint16_t value)
+{
+ assert(devinfo->gen >= 10);
+ brw_inst_set_bits(insn, 124, 109, value);
+}
+/** @} */
+
/**
* Flow control instruction bits:
* @{
FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
/** @} */
+/**
+ * SEND instructions:
+ * @{
+ */
+FC(send_ex_desc_ia_subreg_nr, 82, 80, devinfo->gen >= 9)
+FC(send_src0_address_mode, 79, 79, devinfo->gen >= 9)
+FC(send_sel_reg32_desc, 77, 77, devinfo->gen >= 9)
+FC(send_sel_reg32_ex_desc, 61, 61, devinfo->gen >= 9)
+FC(send_src1_reg_nr, 51, 44, devinfo->gen >= 9)
+FC(send_src1_reg_file, 36, 36, devinfo->gen >= 9)
+FC(send_dst_reg_file, 35, 35, devinfo->gen >= 9)
+/** @} */
+
/* Message descriptor bits */
#define MD(x) ((x) + 96)
+/**
+ * Set the SEND(C) message descriptor immediate.
+ *
+ * This doesn't include the SFID nor the EOT field that were considered to be
+ * part of the message descriptor by ancient versions of the BSpec, because
+ * they are present in the instruction even if the message descriptor is
+ * provided indirectly in the address register, so we want to specify them
+ * separately.
+ */
+static inline void
+brw_inst_set_send_desc(const struct gen_device_info *devinfo,
+ brw_inst *inst, uint32_t value)
+{
+ if (devinfo->gen >= 9) {
+ brw_inst_set_bits(inst, 126, 96, value);
+ assert(value >> 31 == 0);
+ } else if (devinfo->gen >= 5) {
+ brw_inst_set_bits(inst, 124, 96, value);
+ assert(value >> 29 == 0);
+ } else {
+ brw_inst_set_bits(inst, 119, 96, value);
+ assert(value >> 24 == 0);
+ }
+}
+
+/**
+ * Get the SEND(C) message descriptor immediate.
+ *
+ * \sa brw_inst_set_send_desc().
+ */
+static inline uint32_t
+brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ if (devinfo->gen >= 9)
+ return brw_inst_bits(inst, 126, 96);
+ else if (devinfo->gen >= 5)
+ return brw_inst_bits(inst, 124, 96);
+ else
+ return brw_inst_bits(inst, 119, 96);
+}
+
+/**
+ * Set the SEND(C) message extended descriptor immediate.
+ *
+ * This doesn't include the SFID nor the EOT field that were considered to be
+ * part of the extended message descriptor by some versions of the BSpec,
+ * because they are present in the instruction even if the extended message
+ * descriptor is provided indirectly in a register, so we want to specify them
+ * separately.
+ */
+static inline void
+brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
+ brw_inst *inst, uint32_t value)
+{
+ assert(devinfo->gen >= 9);
+ brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
+ brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
+ brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
+ brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
+ assert(GET_BITS(value, 15, 0) == 0);
+}
+
+/**
+ * Set the SENDS(C) message extended descriptor immediate.
+ *
+ * This doesn't include the SFID nor the EOT field that were considered to be
+ * part of the extended message descriptor by some versions of the BSpec,
+ * because they are present in the instruction even if the extended message
+ * descriptor is provided indirectly in a register, so we want to specify them
+ * separately.
+ */
+static inline void
+brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
+ brw_inst *inst, uint32_t value)
+{
+ brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
+ assert(GET_BITS(value, 15, 10) == 0);
+ brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
+ assert(GET_BITS(value, 5, 0) == 0);
+}
+
+/**
+ * Get the SEND(C) message extended descriptor immediate.
+ *
+ * \sa brw_inst_set_send_ex_desc().
+ */
+static inline uint32_t
+brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
+ const brw_inst *inst)
+{
+ assert(devinfo->gen >= 9);
+ return (brw_inst_bits(inst, 94, 91) << 28 |
+ brw_inst_bits(inst, 88, 85) << 24 |
+ brw_inst_bits(inst, 83, 80) << 20 |
+ brw_inst_bits(inst, 67, 64) << 16);
+}
+
+/**
+ * Get the SENDS(C) message extended descriptor immediate.
+ *
+ * \sa brw_inst_set_send_ex_desc().
+ */
+static inline uint32_t
+brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
+ const brw_inst *inst)
+{
+ return (brw_inst_bits(inst, 95, 80) << 16 |
+ brw_inst_bits(inst, 67, 64) << 6);
+}
+
/**
* Fields for SEND messages:
* @{
/* 6: */ 27, 24,
/* 7: */ 27, 24,
/* 8: */ 27, 24)
+FF(null_rt,
+ /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ /* 8: */ 80, 80) /* actually only Gen11+ */
FC(base_mrf, 27, 24, devinfo->gen < 6);
/** @} */
-1, -1, -1, -1, -1, -1,
/* 6: */ MD(16), MD(13),
/* 7: */ MD(17), MD(14),
- /* 8: */ MD(17), MD(14))
+ /* 8: */ MD(18), MD(14))
FF(dp_msg_control,
/* 4: */ MD(11), MD( 8),
/* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
return brw_inst_bits(insn, 127, 96);
}
+static inline uint64_t
+brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
+ const brw_inst *insn)
+{
+ assert(devinfo->gen >= 8);
+ return brw_inst_bits(insn, 127, 64);
+}
+
static inline float
brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
{
/** @} */
+#define REG_TYPE(reg) \
+static inline void \
+brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
+ brw_inst *inst, enum brw_reg_file file, \
+ enum brw_reg_type type) \
+{ \
+ assert(file <= BRW_IMMEDIATE_VALUE); \
+ unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
+ brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
+ brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
+} \
+ \
+static inline enum brw_reg_type \
+brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
+ const brw_inst *inst) \
+{ \
+ unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
+ (unsigned) BRW_GENERAL_REGISTER_FILE : \
+ brw_inst_##reg##_reg_file(devinfo, inst); \
+ unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
+ return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
+}
+
+REG_TYPE(dst)
+REG_TYPE(src0)
+REG_TYPE(src1)
+#undef REG_TYPE
+
+
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
{ \
assert((value & ~0x3ff) == 0); \
if (devinfo->gen >= 8) { \
- brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
- brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
+ assert(GET_BITS(value, 3, 0) == 0); \
+ brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
+ brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
} else { \
- brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
+ brw_inst_set_bits(inst, g4_high, g4_low, value); \
} \
} \
static inline unsigned \
const brw_inst *inst) \
{ \
if (devinfo->gen >= 8) { \
- return brw_inst_bits(inst, g8_high, g8_low) | \
+ return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
} else { \
return brw_inst_bits(inst, g4_high, g4_low); \
* Compared to Align1, these are missing the low 4 bits.
* -Gen 4- ----Gen8----
*/
-BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
-BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
-BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
+BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
+BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
+BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
+BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
+BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
/**
* Fetch a set of contiguous bits from the instruction.
projects / mesa.git / blobdiff