radv: always initialize HTILE when the src layout is UNDEFINED

[mesa.git] / src / intel / compiler / brw_inst.h

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index f60325c1a6b278e475d72762a5b3ae190ce20577..71316f122152f14cf2ee56cfff1bf018632ad7db 100644 (file)
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -455,6 +455,19 @@ FJ(gen4_jump_count, 111,  96, devinfo->gen < 6)
 FC(gen4_pop_count,  115, 112, devinfo->gen < 6)
 /** @} */
 
+/**
+ * SEND instructions:
+ *  @{
+ */
+FC(send_ex_desc_ia_subreg_nr, 82, 80, devinfo->gen >= 9)
+FC(send_src0_address_mode,    79, 79, devinfo->gen >= 9)
+FC(send_sel_reg32_desc,       77, 77, devinfo->gen >= 9)
+FC(send_sel_reg32_ex_desc,    61, 61, devinfo->gen >= 9)
+FC(send_src1_reg_nr,          51, 44, devinfo->gen >= 9)
+FC(send_src1_reg_file,        36, 36, devinfo->gen >= 9)
+FC(send_dst_reg_file,         35, 35, devinfo->gen >= 9)
+/** @} */
+
 /* Message descriptor bits */
 #define MD(x) ((x) + 96)
 
@@ -513,11 +526,21 @@ brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
                           brw_inst *inst, uint32_t value)
 {
    assert(devinfo->gen >= 9);
-   brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
-   brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
-   brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
-   brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
-   assert(GET_BITS(value, 15, 0) == 0);
+   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
+       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC) {
+      brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
+      brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
+      brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
+      brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
+      assert(GET_BITS(value, 15, 0) == 0);
+   } else {
+      assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
+             brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC);
+      brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
+      assert(GET_BITS(value, 15, 10) == 0);
+      brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
+      assert(GET_BITS(value, 5, 0) == 0);
+   }
 }
 
 /**
@@ -530,10 +553,18 @@ brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
                       const brw_inst *inst)
 {
    assert(devinfo->gen >= 9);
-   return (brw_inst_bits(inst, 94, 91) << 28 |
-           brw_inst_bits(inst, 88, 85) << 24 |
-           brw_inst_bits(inst, 83, 80) << 20 |
-           brw_inst_bits(inst, 67, 64) << 16);
+   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
+       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC) {
+      return (brw_inst_bits(inst, 94, 91) << 28 |
+              brw_inst_bits(inst, 88, 85) << 24 |
+              brw_inst_bits(inst, 83, 80) << 20 |
+              brw_inst_bits(inst, 67, 64) << 16);
+   } else {
+      assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
+             brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC);
+      return (brw_inst_bits(inst, 95, 80) << 16 |
+              brw_inst_bits(inst, 67, 64) << 6);
+   }
 }
 
 /**
@@ -956,9 +987,11 @@ brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo,     \
  * Compared to Align1, these are missing the low 4 bits.
  *                     -Gen 4-  ----Gen8----
  */
-BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
-BRW_IA16_ADDR_IMM(src0,  73, 64,  95,  72,  68)
-BRW_IA16_ADDR_IMM(dst,   57, 52,  47,  56,  52)
+BRW_IA16_ADDR_IMM(src1,       105, 96, 121, 104, 100)
+BRW_IA16_ADDR_IMM(src0,        73, 64,  95,  72,  68)
+BRW_IA16_ADDR_IMM(dst,         57, 52,  47,  56,  52)
+BRW_IA16_ADDR_IMM(send_src0,   -1, -1,  78,  72,  68)
+BRW_IA16_ADDR_IMM(send_dst,    -1, -1,  62,  56,  52)
 
 /**
  * Fetch a set of contiguous bits from the instruction.