intel/fs: Remove min_dispatch_width spilling decision from RA

[mesa.git] / src / intel / compiler / brw_ir_vec4.h

diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index bd026eb2aeb2a31237b92efd8f7ce80137139a3d..3f7d9e3e074c844a6001feae50d99b9bdbdafc7e 100644 (file)
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -43,6 +43,7 @@ public:
    src_reg(struct ::brw_reg reg);
 
    bool equals(const src_reg &r) const;
+   bool negative_equals(const src_reg &r) const;
 
    src_reg(class vec4_visitor *v, const struct glsl_type *type);
    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
@@ -192,9 +193,12 @@ offset(dst_reg reg, unsigned width, unsigned delta)
 }
 
 static inline dst_reg
-horiz_offset(dst_reg reg, unsigned delta)
+horiz_offset(const dst_reg &reg, unsigned delta)
 {
-   return byte_offset(reg, delta * type_sz(reg.type));
+   if (is_uniform(src_reg(reg)))
+      return reg;
+   else
+      return byte_offset(reg, delta * type_sz(reg.type));
 }
 
 static inline dst_reg
@@ -281,15 +285,17 @@ public:
    bool sol_final_write; /**< gen6: send commit message */
    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
-   bool is_send_from_grf();
+   bool is_send_from_grf() const;
    unsigned size_read(unsigned arg) const;
    bool can_reswizzle(const struct gen_device_info *devinfo, int dst_writemask,
                       int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
    bool can_do_source_mods(const struct gen_device_info *devinfo);
+   bool can_do_cmod();
    bool can_do_writemask(const struct gen_device_info *devinfo);
    bool can_change_types() const;
    bool has_source_and_destination_hazard() const;
+   unsigned implied_mrf_writes() const;
 
    bool is_align1_partial_write()
    {
@@ -297,7 +303,7 @@ public:
              opcode == VEC4_OPCODE_SET_HIGH_32BIT;
    }
 
-   bool reads_flag()
+   bool reads_flag() const
    {
       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
    }
@@ -323,12 +329,38 @@ public:
       }
    }
 
-   bool writes_flag()
+   bool writes_flag() const
    {
       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
+                                  opcode != BRW_OPCODE_CSEL &&
                                   opcode != BRW_OPCODE_IF &&
                                   opcode != BRW_OPCODE_WHILE));
    }
+
+   bool reads_g0_implicitly() const
+   {
+      switch (opcode) {
+      case SHADER_OPCODE_TEX:
+      case SHADER_OPCODE_TXL:
+      case SHADER_OPCODE_TXD:
+      case SHADER_OPCODE_TXF:
+      case SHADER_OPCODE_TXF_CMS_W:
+      case SHADER_OPCODE_TXF_CMS:
+      case SHADER_OPCODE_TXF_MCS:
+      case SHADER_OPCODE_TXS:
+      case SHADER_OPCODE_TG4:
+      case SHADER_OPCODE_TG4_OFFSET:
+      case SHADER_OPCODE_SAMPLEINFO:
+      case VS_OPCODE_PULL_CONSTANT_LOAD:
+      case GS_OPCODE_SET_PRIMITIVE_ID:
+      case GS_OPCODE_GET_INSTANCE_ID:
+      case SHADER_OPCODE_GEN4_SCRATCH_READ:
+      case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+         return true;
+      default:
+         return false;
+      }
+   }
 };
 
 /**
@@ -404,6 +436,39 @@ regs_read(const vec4_instruction *inst, unsigned i)
                        reg_size);
 }
 
+static inline enum brw_reg_type
+get_exec_type(const vec4_instruction *inst)
+{
+   enum brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
+
+   for (int i = 0; i < 3; i++) {
+      if (inst->src[i].file != BAD_FILE) {
+         const brw_reg_type t = get_exec_type(brw_reg_type(inst->src[i].type));
+         if (type_sz(t) > type_sz(exec_type))
+            exec_type = t;
+         else if (type_sz(t) == type_sz(exec_type) &&
+                  brw_reg_type_is_floating_point(t))
+            exec_type = t;
+      }
+   }
+
+   if (exec_type == BRW_REGISTER_TYPE_B)
+      exec_type = inst->dst.type;
+
+   /* TODO: We need to handle half-float conversions. */
+   assert(exec_type != BRW_REGISTER_TYPE_HF ||
+          inst->dst.type == BRW_REGISTER_TYPE_HF);
+   assert(exec_type != BRW_REGISTER_TYPE_B);
+
+   return exec_type;
+}
+
+static inline unsigned
+get_exec_type_size(const vec4_instruction *inst)
+{
+   return type_sz(get_exec_type(inst));
+}
+
 } /* namespace brw */
 
 #endif