Added few more stubs so that control reaches to DestroyDevice().

[mesa.git] / src / intel / compiler / brw_ir_vec4.h

diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index 95c5119c6c0c2eaafab730004cd4296d6dc73a9f..3f7d9e3e074c844a6001feae50d99b9bdbdafc7e 100644 (file)
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -285,15 +285,17 @@ public:
    bool sol_final_write; /**< gen6: send commit message */
    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
-   bool is_send_from_grf();
+   bool is_send_from_grf() const;
    unsigned size_read(unsigned arg) const;
    bool can_reswizzle(const struct gen_device_info *devinfo, int dst_writemask,
                       int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
    bool can_do_source_mods(const struct gen_device_info *devinfo);
+   bool can_do_cmod();
    bool can_do_writemask(const struct gen_device_info *devinfo);
    bool can_change_types() const;
    bool has_source_and_destination_hazard() const;
+   unsigned implied_mrf_writes() const;
 
    bool is_align1_partial_write()
    {
@@ -301,7 +303,7 @@ public:
              opcode == VEC4_OPCODE_SET_HIGH_32BIT;
    }
 
-   bool reads_flag()
+   bool reads_flag() const
    {
       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
    }
@@ -327,13 +329,38 @@ public:
       }
    }
 
-   bool writes_flag()
+   bool writes_flag() const
    {
       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
                                   opcode != BRW_OPCODE_CSEL &&
                                   opcode != BRW_OPCODE_IF &&
                                   opcode != BRW_OPCODE_WHILE));
    }
+
+   bool reads_g0_implicitly() const
+   {
+      switch (opcode) {
+      case SHADER_OPCODE_TEX:
+      case SHADER_OPCODE_TXL:
+      case SHADER_OPCODE_TXD:
+      case SHADER_OPCODE_TXF:
+      case SHADER_OPCODE_TXF_CMS_W:
+      case SHADER_OPCODE_TXF_CMS:
+      case SHADER_OPCODE_TXF_MCS:
+      case SHADER_OPCODE_TXS:
+      case SHADER_OPCODE_TG4:
+      case SHADER_OPCODE_TG4_OFFSET:
+      case SHADER_OPCODE_SAMPLEINFO:
+      case VS_OPCODE_PULL_CONSTANT_LOAD:
+      case GS_OPCODE_SET_PRIMITIVE_ID:
+      case GS_OPCODE_GET_INSTANCE_ID:
+      case SHADER_OPCODE_GEN4_SCRATCH_READ:
+      case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+         return true;
+      default:
+         return false;
+      }
+   }
 };
 
 /**