anv/entrypoints: Parse entrypoints before extensions/features

[mesa.git] / src / intel / compiler / brw_nir.h

diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 76d7ec89f9b896bb4d26b170ad53269145f42106..3bef99417e787c90d1239a8317487aaa7ca2fdb5 100644 (file)
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -21,7 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-#pragma once
+#ifndef BRW_NIR_H
+#define BRW_NIR_H
 
 #include "brw_reg.h"
 #include "compiler/nir/nir.h"
@@ -94,13 +95,15 @@ void brw_nir_analyze_boolean_resolves(nir_shader *nir);
 nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
                                nir_shader *nir);
 
-bool brw_nir_lower_intrinsics(nir_shader *nir,
-                              struct brw_stage_prog_data *prog_data);
+void
+brw_nir_link_shaders(const struct brw_compiler *compiler,
+                     nir_shader **producer, nir_shader **consumer);
+
+bool brw_nir_lower_cs_intrinsics(nir_shader *nir,
+                                 unsigned dispatch_width);
 void brw_nir_lower_vs_inputs(nir_shader *nir,
-                             bool is_scalar,
-                             bool use_legacy_snorm_formula,
                              const uint8_t *vs_attrib_wa_flags);
-void brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
+void brw_nir_lower_vue_inputs(nir_shader *nir,
                               const struct brw_vue_map *vue_map);
 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
 void brw_nir_lower_fs_inputs(nir_shader *nir,
@@ -117,7 +120,6 @@ nir_shader *brw_postprocess_nir(nir_shader *nir,
                                 bool is_scalar);
 
 bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
-                                         bool use_legacy_snorm_formula,
                                          const uint8_t *attrib_wa_flags);
 
 bool brw_nir_apply_trig_workarounds(nir_shader *nir);
@@ -134,16 +136,27 @@ enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
 
 enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
 
-void brw_nir_setup_glsl_uniforms(nir_shader *shader,
+void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader,
                                  const struct gl_program *prog,
                                  struct brw_stage_prog_data *stage_prog_data,
                                  bool is_scalar);
 
-void brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog,
+void brw_nir_setup_arb_uniforms(void *mem_ctx, nir_shader *shader,
+                                struct gl_program *prog,
                                 struct brw_stage_prog_data *stage_prog_data);
 
+void brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir);
+
+void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
+                                nir_shader *nir,
+                                struct brw_ubo_range out_ranges[4]);
+
 bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 
+nir_shader *brw_nir_optimize(nir_shader *nir,
+                             const struct brw_compiler *compiler,
+                             bool is_scalar);
+
 #define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
 #define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
@@ -152,3 +165,5 @@ bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 #ifdef __cplusplus
 }
 #endif
+
+#endif /* BRW_NIR_H */