intel/eu: Rework opcode description tables to allow efficient look-up by either HW...

[mesa.git] / src / intel / compiler / brw_nir_trig_workarounds.py

diff --git a/src/intel/compiler/brw_nir_trig_workarounds.py b/src/intel/compiler/brw_nir_trig_workarounds.py
index d60e094c625800c951062f67ccd93b0c0e39fa7e..dddadc71da2a709cb5624f867191a1b3e46d36f4 100644 (file)
--- a/src/intel/compiler/brw_nir_trig_workarounds.py
+++ b/src/intel/compiler/brw_nir_trig_workarounds.py
@@ -37,8 +37,8 @@ import argparse
 import sys
 
 TRIG_WORKAROUNDS = [
-    (('fsin', 'x'), ('fmul', ('fsin', 'x'), 0.99997)),
-    (('fcos', 'x'), ('fmul', ('fcos', 'x'), 0.99997)),
+    (('fsin', 'x(is_not_const)'), ('fmul', ('fsin', 'x'), 0.99997)),
+    (('fcos', 'x(is_not_const)'), ('fmul', ('fcos', 'x'), 0.99997)),
 ]