intel: Introducing Amber Lake platform

[mesa.git] / src / intel / compiler / brw_reg_type.c

diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c
index b7fff0867f49fffc39219154fc7c11a7e7d95a1c..60240ba1513666839f054728a5462f542d644b26 100644 (file)
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -23,7 +23,7 @@
 
 #include "brw_reg.h"
 #include "brw_eu_defines.h"
-#include "common/gen_device_info.h"
+#include "dev/gen_device_info.h"
 
 #define INVALID (-1)
 
@@ -40,6 +40,19 @@ enum hw_reg_type {
    BRW_HW_REG_TYPE_B   = 5,
    GEN7_HW_REG_TYPE_DF = 6,
    GEN8_HW_REG_TYPE_HF = 10,
+
+   GEN11_HW_REG_TYPE_UD = 0,
+   GEN11_HW_REG_TYPE_D  = 1,
+   GEN11_HW_REG_TYPE_UW = 2,
+   GEN11_HW_REG_TYPE_W  = 3,
+   GEN11_HW_REG_TYPE_UB = 4,
+   GEN11_HW_REG_TYPE_B  = 5,
+   GEN11_HW_REG_TYPE_UQ = 6,
+   GEN11_HW_REG_TYPE_Q  = 7,
+   GEN11_HW_REG_TYPE_HF = 8,
+   GEN11_HW_REG_TYPE_F  = 9,
+   GEN11_HW_REG_TYPE_DF = 10,
+   GEN11_HW_REG_TYPE_NF = 11,
 };
 
 enum hw_imm_type {
@@ -56,12 +69,27 @@ enum hw_imm_type {
    BRW_HW_IMM_TYPE_V   = 6,
    GEN8_HW_IMM_TYPE_DF = 10,
    GEN8_HW_IMM_TYPE_HF = 11,
+
+   GEN11_HW_IMM_TYPE_UD = 0,
+   GEN11_HW_IMM_TYPE_D  = 1,
+   GEN11_HW_IMM_TYPE_UW = 2,
+   GEN11_HW_IMM_TYPE_W  = 3,
+   GEN11_HW_IMM_TYPE_UV = 4,
+   GEN11_HW_IMM_TYPE_V  = 5,
+   GEN11_HW_IMM_TYPE_UQ = 6,
+   GEN11_HW_IMM_TYPE_Q  = 7,
+   GEN11_HW_IMM_TYPE_HF = 8,
+   GEN11_HW_IMM_TYPE_F  = 9,
+   GEN11_HW_IMM_TYPE_DF = 10,
+   GEN11_HW_IMM_TYPE_VF = 11,
 };
 
-static const struct {
+static const struct hw_type {
    enum hw_reg_type reg_type;
    enum hw_imm_type imm_type;
 } gen4_hw_type[] = {
+   [0 ... BRW_REGISTER_TYPE_LAST] = {     INVALID, INVALID             },
+
    [BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
    [BRW_REGISTER_TYPE_F]  = { BRW_HW_REG_TYPE_F,   BRW_HW_IMM_TYPE_F   },
    [BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
@@ -77,6 +105,23 @@ static const struct {
    [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB,  INVALID             },
    [BRW_REGISTER_TYPE_V]  = { INVALID,             BRW_HW_IMM_TYPE_V   },
    [BRW_REGISTER_TYPE_UV] = { INVALID,             BRW_HW_IMM_TYPE_UV  },
+}, gen11_hw_type[] = {
+   [BRW_REGISTER_TYPE_NF] = { GEN11_HW_REG_TYPE_NF, INVALID              },
+   [BRW_REGISTER_TYPE_DF] = { GEN11_HW_REG_TYPE_DF, GEN11_HW_IMM_TYPE_DF },
+   [BRW_REGISTER_TYPE_F]  = { GEN11_HW_REG_TYPE_F,  GEN11_HW_IMM_TYPE_F  },
+   [BRW_REGISTER_TYPE_HF] = { GEN11_HW_REG_TYPE_HF, GEN11_HW_IMM_TYPE_HF },
+   [BRW_REGISTER_TYPE_VF] = { INVALID,              GEN11_HW_IMM_TYPE_VF },
+
+   [BRW_REGISTER_TYPE_Q]  = { GEN11_HW_REG_TYPE_Q,  GEN11_HW_IMM_TYPE_Q  },
+   [BRW_REGISTER_TYPE_UQ] = { GEN11_HW_REG_TYPE_UQ, GEN11_HW_IMM_TYPE_UQ },
+   [BRW_REGISTER_TYPE_D]  = { GEN11_HW_REG_TYPE_D,  GEN11_HW_IMM_TYPE_D  },
+   [BRW_REGISTER_TYPE_UD] = { GEN11_HW_REG_TYPE_UD, GEN11_HW_IMM_TYPE_UD },
+   [BRW_REGISTER_TYPE_W]  = { GEN11_HW_REG_TYPE_W,  GEN11_HW_IMM_TYPE_W  },
+   [BRW_REGISTER_TYPE_UW] = { GEN11_HW_REG_TYPE_UW, GEN11_HW_IMM_TYPE_UW },
+   [BRW_REGISTER_TYPE_B]  = { GEN11_HW_REG_TYPE_B,  INVALID              },
+   [BRW_REGISTER_TYPE_UB] = { GEN11_HW_REG_TYPE_UB, INVALID              },
+   [BRW_REGISTER_TYPE_V]  = { INVALID,              GEN11_HW_IMM_TYPE_V  },
+   [BRW_REGISTER_TYPE_UV] = { INVALID,              GEN11_HW_IMM_TYPE_UV },
 };
 
 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
@@ -98,6 +143,7 @@ enum hw_3src_reg_type {
    GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
    GEN10_ALIGN1_3SRC_REG_TYPE_F  = 0b001,
    GEN10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
+   GEN11_ALIGN1_3SRC_REG_TYPE_NF = 0b011,
    /** @} */
 
    /** When ExecutionDatatype is 0: @{ */
@@ -124,6 +170,7 @@ static const struct hw_3src_type {
 #define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
    [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
 
+   [BRW_REGISTER_TYPE_NF] = { GEN11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
    [BRW_REGISTER_TYPE_DF] = { GEN10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
    [BRW_REGISTER_TYPE_F]  = { GEN10_ALIGN1_3SRC_REG_TYPE_F,  E(FLOAT) },
    [BRW_REGISTER_TYPE_HF] = { GEN10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
@@ -147,14 +194,25 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
                         enum brw_reg_file file,
                         enum brw_reg_type type)
 {
-   assert(type < ARRAY_SIZE(gen4_hw_type));
+   const struct hw_type *table;
+
+   if (devinfo->gen >= 11) {
+      assert(type < ARRAY_SIZE(gen11_hw_type));
+      table = gen11_hw_type;
+   } else {
+      assert(type < ARRAY_SIZE(gen4_hw_type));
+      table = gen4_hw_type;
+   }
+
+   assert(devinfo->has_64bit_types || brw_reg_type_to_size(type) < 8 ||
+          type == BRW_REGISTER_TYPE_NF);
 
    if (file == BRW_IMMEDIATE_VALUE) {
-      assert(gen4_hw_type[type].imm_type != (enum hw_imm_type)INVALID);
-      return gen4_hw_type[type].imm_type;
+      assert(table[type].imm_type != (enum hw_imm_type)INVALID);
+      return table[type].imm_type;
    } else {
-      assert(gen4_hw_type[type].reg_type != (enum hw_reg_type)INVALID);
-      return gen4_hw_type[type].reg_type;
+      assert(table[type].reg_type != (enum hw_reg_type)INVALID);
+      return table[type].reg_type;
    }
 }
 
@@ -167,15 +225,23 @@ enum brw_reg_type
 brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
                         enum brw_reg_file file, unsigned hw_type)
 {
+   const struct hw_type *table;
+
+   if (devinfo->gen >= 11) {
+      table = gen11_hw_type;
+   } else {
+      table = gen4_hw_type;
+   }
+
    if (file == BRW_IMMEDIATE_VALUE) {
       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
-         if (gen4_hw_type[i].imm_type == (enum hw_imm_type)hw_type) {
+         if (table[i].imm_type == (enum hw_imm_type)hw_type) {
             return i;
          }
       }
    } else {
       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
-         if (gen4_hw_type[i].reg_type == (enum hw_reg_type)hw_type) {
+         if (table[i].reg_type == (enum hw_reg_type)hw_type) {
             return i;
          }
       }
@@ -249,6 +315,7 @@ unsigned
 brw_reg_type_to_size(enum brw_reg_type type)
 {
    static const unsigned type_size[] = {
+      [BRW_REGISTER_TYPE_NF] = 8,
       [BRW_REGISTER_TYPE_DF] = 8,
       [BRW_REGISTER_TYPE_F]  = 4,
       [BRW_REGISTER_TYPE_HF] = 2,
@@ -278,6 +345,7 @@ const char *
 brw_reg_type_to_letters(enum brw_reg_type type)
 {
    static const char letters[][3] = {
+      [BRW_REGISTER_TYPE_NF] = "NF",
       [BRW_REGISTER_TYPE_DF] = "DF",
       [BRW_REGISTER_TYPE_F]  = "F",
       [BRW_REGISTER_TYPE_HF] = "HF",