/* Nothing to do. */
return false;
case BRW_REGISTER_TYPE_F:
- sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
+ sat_imm.f = SATURATE(imm.f);
break;
case BRW_REGISTER_TYPE_DF:
- sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
+ sat_imm.df = SATURATE(imm.df);
break;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
nir(shader),
stage_prog_data(stage_prog_data),
mem_ctx(mem_ctx),
- cfg(NULL),
+ cfg(NULL), idom_analysis(this),
stage(shader->info.stage)
{
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
case BRW_OPCODE_ADD:
case BRW_OPCODE_ASR:
case BRW_OPCODE_AVG:
+ case BRW_OPCODE_CSEL:
case BRW_OPCODE_DP2:
case BRW_OPCODE_DP3:
case BRW_OPCODE_DP4:
}
void
-backend_shader::dump_instructions()
+backend_shader::dump_instructions() const
{
dump_instructions(NULL);
}
void
-backend_shader::dump_instructions(const char *name)
+backend_shader::dump_instructions(const char *name) const
{
FILE *file = stderr;
if (name && geteuid() != 0) {
{
if (this->cfg)
return;
- cfg = new(mem_ctx) cfg_t(&this->instructions);
+ cfg = new(mem_ctx) cfg_t(this, &this->instructions);
}
void
backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
{
+ idom_analysis.invalidate(c);
}
extern "C" const unsigned *
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
nir->info.outputs_written,
- nir->info.separate_shader);
+ nir->info.separate_shader, 1);
unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx,
- &prog_data->base.base, v.shader_stats, false,
- MESA_SHADER_TESS_EVAL);
+ &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
"%s tessellation evaluation shader %s",
nir->info.name));
}
- g.generate_code(v.cfg, 8, stats);
+ g.generate_code(v.cfg, 8, v.shader_stats,
+ v.performance_analysis.require(), stats);
assembly = g.get_assembly();
} else {
v.dump_instructions();
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
- &prog_data->base, v.cfg, stats);
+ &prog_data->base, v.cfg,
+ v.performance_analysis.require(),
+ stats);
}
return assembly;