intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).

[mesa.git] / src / intel / compiler / brw_shader.h

diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index 89e2776776eeb66376fde1a714bda533f01478a6..61b5cd6fad38ba4449829aa9dba40391e9abbd6c 100644 (file)
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -21,7 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-#pragma once
+#ifndef BRW_SHADER_H
+#define BRW_SHADER_H
 
 #include <stdint.h>
 #include "brw_reg.h"
@@ -58,6 +59,7 @@ struct backend_reg : private brw_reg
    }
 
    bool equals(const backend_reg &r) const;
+   bool negative_equals(const backend_reg &r) const;
 
    bool is_zero() const;
    bool is_one() const;
@@ -87,6 +89,8 @@ struct backend_reg : private brw_reg
    using brw_reg::f;
    using brw_reg::d;
    using brw_reg::ud;
+   using brw_reg::d64;
+   using brw_reg::u64;
 };
 #endif
 
@@ -152,8 +156,11 @@ struct backend_instruction {
 
    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
    uint8_t mlen; /**< SEND message length */
+   uint8_t ex_mlen; /**< SENDS extended message length */
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint8_t target; /**< MRT target. */
+   uint8_t sfid; /**< SFID for SEND instructions */
+   uint32_t desc; /**< SEND[S] message descriptor immediate */
    unsigned size_written; /**< Data written to the destination register in bytes. */
 
    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
@@ -166,11 +173,15 @@ struct backend_instruction {
    bool no_dd_check:1;
    bool saturate:1;
    bool shadow_compare:1;
+   bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */
+   bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */
+   bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */
+   bool eot:1;
 
-   /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
+   /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
     * mod and predication.
     */
-   unsigned flag_subreg:1;
+   unsigned flag_subreg:2;
 
    /** The number of hardware registers used for a message header. */
    uint8_t header_size;
@@ -195,6 +206,7 @@ protected:
                   struct brw_stage_prog_data *stage_prog_data);
 
 public:
+   virtual ~backend_shader();
 
    const struct brw_compiler *compiler;
    void *log_data; /* Passed to compiler->*_log functions */
@@ -231,8 +243,7 @@ public:
    virtual void invalidate_live_intervals() = 0;
 };
 
-bool brw_texture_offset(int *offsets,
-                        unsigned num_components,
+bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
                         uint32_t *offset_bits);
 
 #else
@@ -283,8 +294,8 @@ struct brw_gs_compile
    unsigned control_data_header_size_bits;
 };
 
-unsigned get_atomic_counter_op(nir_intrinsic_op op);
-
 #ifdef __cplusplus
 }
 #endif
+
+#endif /* BRW_SHADER_H */