intel/eu: Rework opcode description tables to allow efficient look-up by either HW...

[mesa.git] / src / intel / compiler / gen6_gs_visitor.cpp

diff --git a/src/intel/compiler/gen6_gs_visitor.cpp b/src/intel/compiler/gen6_gs_visitor.cpp
index c9571cce6fde3c6cfa9242498e2fb31c1240590e..2742fbacfa1d062b063b1dd79467077ed0bf03d3 100644 (file)
--- a/src/intel/compiler/gen6_gs_visitor.cpp
+++ b/src/intel/compiler/gen6_gs_visitor.cpp
@@ -274,8 +274,8 @@ gen6_gs_visitor::emit_urb_write_header(int mrf)
    emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, mrf), flags_data);
 }
 
-static int
-align_interleaved_urb_mlen(int mlen)
+static unsigned
+align_interleaved_urb_mlen(unsigned mlen)
 {
    /* URB data written (does not include the message header reg) must
     * be a multiple of 256 bits, or 2 VS registers.  See vol5c.5,