intel: Implement Gen12 workaround for array textures of size 1

[mesa.git] / src / intel / compiler / meson.build

diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index 3b1445613729ddcf568a2cca1ad7f89c43ae52a3..4a4a76cece8d2cbcec6bc5fb51b90af3289d7295 100644 (file)
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -83,6 +83,7 @@ libintel_compiler_files = files(
   'brw_nir_lower_mem_access_bit_sizes.c',
   'brw_nir_opt_peephole_ffma.c',
   'brw_nir_tcs_workarounds.c',
+  'brw_nir_clamp_image_1d_2d_array_sizes.c',
   'brw_packed_float.c',
   'brw_predicated_break.cpp',
   'brw_reg.h',