radv: always initialize HTILE when the src layout is UNDEFINED

[mesa.git] / src / intel / compiler / meson.build

diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index 19e5926a0d92c6d6d079e8a985b89b192380da15..21614c5baf99a424a02a84e5ee9116931629418e 100644 (file)
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -55,15 +55,13 @@ libintel_compiler_files = files(
   'brw_fs.h',
   'brw_fs_live_variables.cpp',
   'brw_fs_live_variables.h',
-  'brw_fs_lower_conversions.cpp',
   'brw_fs_lower_pack.cpp',
+  'brw_fs_lower_regioning.cpp',
   'brw_fs_nir.cpp',
   'brw_fs_reg_allocate.cpp',
   'brw_fs_register_coalesce.cpp',
   'brw_fs_saturate_propagation.cpp',
   'brw_fs_sel_peephole.cpp',
-  'brw_fs_surface_builder.cpp',
-  'brw_fs_surface_builder.h',
   'brw_fs_validate.cpp',
   'brw_fs_visitor.cpp',
   'brw_inst.h',
@@ -77,6 +75,8 @@ libintel_compiler_files = files(
   'brw_nir_analyze_ubo_ranges.c',
   'brw_nir_attribute_workarounds.c',
   'brw_nir_lower_cs_intrinsics.c',
+  'brw_nir_lower_image_load_store.c',
+  'brw_nir_lower_mem_access_bit_sizes.c',
   'brw_nir_opt_peephole_ffma.c',
   'brw_nir_tcs_workarounds.c',
   'brw_packed_float.c',
@@ -122,7 +122,7 @@ brw_nir_trig = custom_target(
   input : 'brw_nir_trig_workarounds.py',
   output : 'brw_nir_trig_workarounds.c',
   command : [
-    prog_python2, '@INPUT@',
+    prog_python, '@INPUT@',
     '-p', join_paths(meson.source_root(), 'src/compiler/nir/'),
   ],
   depend_files : nir_algebraic_py,
@@ -131,11 +131,11 @@ brw_nir_trig = custom_target(
 
 libintel_compiler = static_library(
   'intel_compiler',
-  [libintel_compiler_files, brw_nir_trig, nir_opcodes_h, nir_builder_opcodes_h,
-   ir_expression_operation_h],
-  include_directories : [inc_common, inc_intel, inc_nir],
+  [libintel_compiler_files, brw_nir_trig, ir_expression_operation_h],
+  include_directories : [inc_common, inc_intel],
   c_args : [c_vis_args, no_override_init_args],
   cpp_args : [cpp_vis_args],
+  dependencies : idep_nir_headers,
   build_by_default : false,
 )
 
@@ -144,18 +144,20 @@ if with_tests
   foreach t : ['fs_cmod_propagation', 'fs_copy_propagation',
                'fs_saturate_propagation', 'vf_float_conversions',
                'vec4_register_coalesce', 'vec4_copy_propagation',
-               'vec4_cmod_propagation', 'eu_compact', 'eu_validate']
+               'vec4_cmod_propagation', 'vec4_dead_code_eliminate',
+               'eu_compact', 'eu_validate']
     test(
       t,
       executable(
-        [t, nir_opcodes_h, ir_expression_operation_h],
+        [t, ir_expression_operation_h],
         'test_@0@.cpp'.format(t),
         include_directories : [inc_common, inc_intel],
         link_with : [
-          libintel_compiler, libintel_common, libnir, libmesa_util, libisl,
+          libintel_compiler, libintel_common, libintel_dev, libmesa_util, libisl,
         ],
-        dependencies : [dep_thread, dep_dl, idep_gtest],
-      )
+        dependencies : [dep_thread, dep_dl, idep_gtest, idep_nir],
+      ),
+      suite : ['intel'],
     )
   endforeach
 endif