i965/vec4: Handle 16-bit types at type_size_xvec4

[mesa.git] / src / intel / compiler / test_eu_validate.cpp

diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp
index b147b6b227e5b9fe0e5158f5e40b94aec54f0e1f..cb2fcd3d40f64dee5a98b494851f492dbbe30c03 100644 (file)
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -113,20 +113,20 @@ static bool
 validate(struct brw_codegen *p)
 {
    const bool print = getenv("TEST_DEBUG");
-   struct disasm_info disasm = disasm_initialize(p->devinfo, NULL);
+   struct disasm_info *disasm = disasm_initialize(p->devinfo, NULL);
 
    if (print) {
-      disasm_new_inst_group(&disasm, 0);
-      disasm_new_inst_group(&disasm, p->next_insn_offset);
+      disasm_new_inst_group(disasm, 0);
+      disasm_new_inst_group(disasm, p->next_insn_offset);
    }
 
    bool ret = brw_validate_instructions(p->devinfo, p->store, 0,
-                                        p->next_insn_offset, &disasm);
+                                        p->next_insn_offset, disasm);
 
    if (print) {
-      dump_assembly(p->store, &disasm);
+      dump_assembly(p->store, disasm);
    }
-   ralloc_free(disasm.mem_ctx);
+   ralloc_free(disasm);
 
    return ret;
 }