*/
#include <assert.h>
+#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "gen_device_info.h"
#include "compiler/shader_enums.h"
+#include "intel/common/gen_gem.h"
#include "util/bitscan.h"
#include "util/macros.h"
-#include <i915_drm.h>
+#include "drm-uapi/i915_drm.h"
/**
* Get the PCI ID for the device name.
{ "skl", 0x1912 },
{ "bxt", 0x5A85 },
{ "kbl", 0x5912 },
+ { "aml", 0x591C },
{ "glk", 0x3185 },
{ "cfl", 0x3E9B },
+ { "whl", 0x3EA1 },
+ { "cml", 0x9b41 },
{ "cnl", 0x5a52 },
{ "icl", 0x8a52 },
};
.size = 256,
},
.timestamp_frequency = 12500000,
+ .simulator_id = -1,
};
static const struct gen_device_info gen_device_info_g4x = {
.size = 384,
},
.timestamp_frequency = 12500000,
+ .simulator_id = -1,
};
static const struct gen_device_info gen_device_info_ilk = {
.size = 1024,
},
.timestamp_frequency = 12500000,
+ .simulator_id = -1,
};
static const struct gen_device_info gen_device_info_snb_gt1 = {
},
},
.timestamp_frequency = 12500000,
+ .simulator_id = -1,
};
static const struct gen_device_info gen_device_info_snb_gt2 = {
},
},
.timestamp_frequency = 12500000,
+ .simulator_id = -1,
};
#define GEN7_FEATURES \
[MESA_SHADER_GEOMETRY] = 192,
},
},
+ .simulator_id = 7,
};
static const struct gen_device_info gen_device_info_ivb_gt2 = {
[MESA_SHADER_GEOMETRY] = 320,
},
},
+ .simulator_id = 7,
};
static const struct gen_device_info gen_device_info_byt = {
[MESA_SHADER_GEOMETRY] = 192,
},
},
+ .simulator_id = 10,
};
#define HSW_FEATURES \
[MESA_SHADER_GEOMETRY] = 256,
},
},
+ .simulator_id = 9,
};
static const struct gen_device_info gen_device_info_hsw_gt2 = {
[MESA_SHADER_GEOMETRY] = 640,
},
},
+ .simulator_id = 9,
};
static const struct gen_device_info gen_device_info_hsw_gt3 = {
[MESA_SHADER_GEOMETRY] = 640,
},
},
+ .simulator_id = 9,
};
/* It's unclear how well supported sampling from the hiz buffer is on GEN8,
.has_64bit_types = true, \
.supports_simd16_3src = true, \
.has_surface_tile_offset = true, \
+ .num_thread_per_eu = 7, \
.max_vs_threads = 504, \
.max_tcs_threads = 504, \
.max_tes_threads = 504, \
.num_slices = 1,
.num_subslices = { 2, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 2,
.max_cs_threads = 42,
.urb = {
[MESA_SHADER_TESS_EVAL] = 1536,
[MESA_SHADER_GEOMETRY] = 960,
},
- }
+ },
+ .simulator_id = 11,
};
static const struct gen_device_info gen_device_info_bdw_gt2 = {
.num_slices = 1,
.num_subslices = { 3, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 4,
.max_cs_threads = 56,
.urb = {
[MESA_SHADER_TESS_EVAL] = 1536,
[MESA_SHADER_GEOMETRY] = 960,
},
- }
+ },
+ .simulator_id = 11,
};
static const struct gen_device_info gen_device_info_bdw_gt3 = {
.num_slices = 2,
.num_subslices = { 3, 3, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 8,
.max_cs_threads = 56,
.urb = {
[MESA_SHADER_TESS_EVAL] = 1536,
[MESA_SHADER_GEOMETRY] = 960,
},
- }
+ },
+ .simulator_id = 11,
};
static const struct gen_device_info gen_device_info_chv = {
.num_slices = 1,
.num_subslices = { 2, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 80,
.max_tcs_threads = 80,
[MESA_SHADER_TESS_EVAL] = 384,
[MESA_SHADER_GEOMETRY] = 256,
},
- }
+ },
+ .simulator_id = 13,
};
#define GEN9_HW_INFO \
#define GEN9_FEATURES \
GEN8_FEATURES, \
GEN9_HW_INFO, \
- .has_sample_with_hiz = true, \
- .num_thread_per_eu = 7
+ .has_sample_with_hiz = true
static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
.num_eu_per_subslice = 6,
.l3_banks = 2,
.urb.size = 192,
+ /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+ * leading to some vertices to go missing if we use too much URB.
+ */
+ .urb.max_entries[MESA_SHADER_VERTEX] = 928,
+ .simulator_id = 12,
};
static const struct gen_device_info gen_device_info_skl_gt2 = {
.num_subslices = { 3, },
.num_eu_per_subslice = 8,
.l3_banks = 4,
+ .simulator_id = 12,
};
static const struct gen_device_info gen_device_info_skl_gt3 = {
.num_subslices = { 3, 3, },
.num_eu_per_subslice = 8,
.l3_banks = 8,
+ .simulator_id = 12,
};
static const struct gen_device_info gen_device_info_skl_gt4 = {
* only 1008KB of this will be used."
*/
.urb.size = 1008 / 3,
+ .simulator_id = 12,
};
static const struct gen_device_info gen_device_info_bxt = {
GEN9_LP_FEATURES_3X6,
.is_broxton = true,
.l3_banks = 2,
+ .simulator_id = 14,
};
static const struct gen_device_info gen_device_info_bxt_2x6 = {
GEN9_LP_FEATURES_2X6,
.is_broxton = true,
.l3_banks = 1,
+ .simulator_id = 14,
};
/*
* Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
.num_subslices = { 2, },
.num_eu_per_subslice = 6,
.l3_banks = 2,
+ /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+ * leading to some vertices to go missing if we use too much URB.
+ */
+ .urb.max_entries[MESA_SHADER_VERTEX] = 928,
+ .simulator_id = 16,
};
static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
.num_subslices = { 3, },
.num_eu_per_subslice = 6,
.l3_banks = 4,
+ .simulator_id = 16,
};
static const struct gen_device_info gen_device_info_kbl_gt2 = {
.num_subslices = { 3, },
.num_eu_per_subslice = 8,
.l3_banks = 4,
+ .simulator_id = 16,
};
static const struct gen_device_info gen_device_info_kbl_gt3 = {
.num_subslices = { 3, 3, },
.num_eu_per_subslice = 8,
.l3_banks = 8,
+ .simulator_id = 16,
};
static const struct gen_device_info gen_device_info_kbl_gt4 = {
.num_subslices = { 3, 3, 3, },
.num_eu_per_subslice = 8,
.l3_banks = 12,
+ .simulator_id = 16,
};
static const struct gen_device_info gen_device_info_glk = {
GEN9_LP_FEATURES_3X6,
.is_geminilake = true,
.l3_banks = 2,
+ .simulator_id = 17,
};
-/*TODO: Initialize l3_banks when we know the number. */
static const struct gen_device_info gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6,
.is_geminilake = true,
+ .l3_banks = 2,
+ .simulator_id = 17,
};
static const struct gen_device_info gen_device_info_cfl_gt1 = {
.num_subslices = { 2, },
.num_eu_per_subslice = 6,
.l3_banks = 2,
+ .urb.size = 192,
+ /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+ * leading to some vertices to go missing if we use too much URB.
+ */
+ .urb.max_entries[MESA_SHADER_VERTEX] = 928,
+ .simulator_id = 24,
};
static const struct gen_device_info gen_device_info_cfl_gt2 = {
GEN9_FEATURES,
.num_subslices = { 3, },
.num_eu_per_subslice = 8,
.l3_banks = 4,
+ .simulator_id = 24,
};
static const struct gen_device_info gen_device_info_cfl_gt3 = {
.num_subslices = { 3, 3, },
.num_eu_per_subslice = 8,
.l3_banks = 8,
+ .simulator_id = 24,
};
#define GEN10_HW_INFO \
/* GT0.5 */
GEN10_FEATURES(1, 1, subslices(2), 2),
.is_cannonlake = true,
+ .simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_3x8 = {
/* GT1 */
GEN10_FEATURES(1, 1, subslices(3), 3),
.is_cannonlake = true,
+ .simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_4x8 = {
/* GT 1.5 */
GEN10_FEATURES(1, 2, subslices(2, 2), 6),
.is_cannonlake = true,
+ .simulator_id = 15,
};
static const struct gen_device_info gen_device_info_cnl_5x8 = {
/* GT2 */
GEN10_FEATURES(2, 2, subslices(3, 2), 6),
.is_cannonlake = true,
+ .simulator_id = 15,
};
#define GEN11_HW_INFO \
.max_gs_threads = 224, \
.max_tcs_threads = 224, \
.max_tes_threads = 364, \
- .max_cs_threads = 56, \
- .urb = { \
- .size = 1024, \
- .min_entries = { \
- [MESA_SHADER_VERTEX] = 64, \
- [MESA_SHADER_TESS_EVAL] = 34, \
- }, \
- .max_entries = { \
- [MESA_SHADER_VERTEX] = 2384, \
- [MESA_SHADER_TESS_CTRL] = 1032, \
- [MESA_SHADER_TESS_EVAL] = 2384, \
- [MESA_SHADER_GEOMETRY] = 1032, \
- }, \
- }
+ .max_cs_threads = 56
#define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
.num_subslices = _subslices, \
.num_eu_per_subslice = 8
+#define GEN11_URB_MIN_MAX_ENTRIES \
+ .min_entries = { \
+ [MESA_SHADER_VERTEX] = 64, \
+ [MESA_SHADER_TESS_EVAL] = 34, \
+ }, \
+ .max_entries = { \
+ [MESA_SHADER_VERTEX] = 2384, \
+ [MESA_SHADER_TESS_CTRL] = 1032, \
+ [MESA_SHADER_TESS_EVAL] = 2384, \
+ [MESA_SHADER_GEOMETRY] = 1032, \
+ }
+
static const struct gen_device_info gen_device_info_icl_8x8 = {
GEN11_FEATURES(2, 1, subslices(8), 8),
+ .urb = {
+ .size = 1024,
+ GEN11_URB_MIN_MAX_ENTRIES,
+ },
+ .simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_6x8 = {
GEN11_FEATURES(1, 1, subslices(6), 6),
+ .urb = {
+ .size = 768,
+ GEN11_URB_MIN_MAX_ENTRIES,
+ },
+ .simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_4x8 = {
GEN11_FEATURES(1, 1, subslices(4), 6),
+ .urb = {
+ .size = 768,
+ GEN11_URB_MIN_MAX_ENTRIES,
+ },
+ .simulator_id = 19,
};
static const struct gen_device_info gen_device_info_icl_1x8 = {
GEN11_FEATURES(1, 1, subslices(1), 6),
+ .urb = {
+ .size = 768,
+ GEN11_URB_MIN_MAX_ENTRIES,
+ },
+ .simulator_id = 19,
+};
+
+static const struct gen_device_info gen_device_info_ehl_4x8 = {
+ GEN11_FEATURES(1, 1, subslices(4), 4),
+ .urb = {
+ .size = 512,
+ .min_entries = {
+ [MESA_SHADER_VERTEX] = 64,
+ [MESA_SHADER_TESS_EVAL] = 34,
+ },
+ .max_entries = {
+ [MESA_SHADER_VERTEX] = 2384,
+ [MESA_SHADER_TESS_CTRL] = 1032,
+ [MESA_SHADER_TESS_EVAL] = 2384,
+ [MESA_SHADER_GEOMETRY] = 1032,
+ },
+ },
+ .disable_ccs_repack = true,
+ .simulator_id = 28,
+};
+
+/* FIXME: Verfiy below entries when more information is available for this SKU.
+ */
+static const struct gen_device_info gen_device_info_ehl_4x4 = {
+ GEN11_FEATURES(1, 1, subslices(4), 4),
+ .urb = {
+ .size = 512,
+ .min_entries = {
+ [MESA_SHADER_VERTEX] = 64,
+ [MESA_SHADER_TESS_EVAL] = 34,
+ },
+ .max_entries = {
+ [MESA_SHADER_VERTEX] = 2384,
+ [MESA_SHADER_TESS_CTRL] = 1032,
+ [MESA_SHADER_TESS_EVAL] = 2384,
+ [MESA_SHADER_GEOMETRY] = 1032,
+ },
+ },
+ .disable_ccs_repack = true,
+ .num_eu_per_subslice = 4,
+ .simulator_id = 28,
+};
+
+/* FIXME: Verfiy below entries when more information is available for this SKU.
+ */
+static const struct gen_device_info gen_device_info_ehl_2x4 = {
+ GEN11_FEATURES(1, 1, subslices(2), 4),
+ .urb = {
+ .size = 512,
+ .min_entries = {
+ [MESA_SHADER_VERTEX] = 64,
+ [MESA_SHADER_TESS_EVAL] = 34,
+ },
+ .max_entries = {
+ [MESA_SHADER_VERTEX] = 2384,
+ [MESA_SHADER_TESS_CTRL] = 1032,
+ [MESA_SHADER_TESS_EVAL] = 2384,
+ [MESA_SHADER_GEOMETRY] = 1032,
+ },
+ },
+ .disable_ccs_repack = true,
+ .num_eu_per_subslice =4,
+ .simulator_id = 28,
};
static void
}
}
-void
+bool
gen_device_info_update_from_masks(struct gen_device_info *devinfo,
uint32_t slice_mask,
uint32_t subslice_mask,
uint32_t n_eus)
{
- struct {
- struct drm_i915_query_topology_info base;
- uint8_t data[100];
- } topology;
+ struct drm_i915_query_topology_info *topology;
assert((slice_mask & 0xff) == slice_mask);
- memset(&topology, 0, sizeof(topology));
+ size_t data_length = 100;
+
+ topology = calloc(1, sizeof(*topology) + data_length);
+ if (!topology)
+ return false;
- topology.base.max_slices = util_last_bit(slice_mask);
- topology.base.max_subslices = util_last_bit(subslice_mask);
+ topology->max_slices = util_last_bit(slice_mask);
+ topology->max_subslices = util_last_bit(subslice_mask);
- topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
- topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
+ topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
+ topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
uint32_t n_subslices = __builtin_popcount(slice_mask) *
__builtin_popcount(subslice_mask);
uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
- topology.base.eu_offset = topology.base.subslice_offset +
- DIV_ROUND_UP(topology.base.max_subslices, 8);
- topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
+ topology->eu_offset = topology->subslice_offset +
+ DIV_ROUND_UP(topology->max_subslices, 8);
+ topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
/* Set slice mask in topology */
- for (int b = 0; b < topology.base.subslice_offset; b++)
- topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
+ for (int b = 0; b < topology->subslice_offset; b++)
+ topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
- for (int s = 0; s < topology.base.max_slices; s++) {
+ for (int s = 0; s < topology->max_slices; s++) {
/* Set subslice mask in topology */
- for (int b = 0; b < topology.base.subslice_stride; b++) {
- int subslice_offset = topology.base.subslice_offset +
- s * topology.base.subslice_stride + b;
+ for (int b = 0; b < topology->subslice_stride; b++) {
+ int subslice_offset = topology->subslice_offset +
+ s * topology->subslice_stride + b;
- topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
+ topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
}
/* Set eu mask in topology */
- for (int ss = 0; ss < topology.base.max_subslices; ss++) {
- for (int b = 0; b < topology.base.eu_stride; b++) {
- int eu_offset = topology.base.eu_offset +
- (s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
+ for (int ss = 0; ss < topology->max_subslices; ss++) {
+ for (int b = 0; b < topology->eu_stride; b++) {
+ int eu_offset = topology->eu_offset +
+ (s * topology->max_subslices + ss) * topology->eu_stride + b;
- topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
+ topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
}
}
}
- gen_device_info_update_from_topology(devinfo, &topology.base);
+ gen_device_info_update_from_topology(devinfo, topology);
+ free(topology);
+
+ return true;
}
static void
devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
}
+static bool
+getparam(int fd, uint32_t param, int *value)
+{
+ int tmp;
+
+ struct drm_i915_getparam gp = {
+ .param = param,
+ .value = &tmp,
+ };
+
+ int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ if (ret != 0)
+ return false;
+
+ *value = tmp;
+ return true;
+}
+
bool
gen_get_device_info(int devid, struct gen_device_info *devinfo)
{
case id: *devinfo = gen_device_info_##family; break;
#include "pci_ids/i965_pci_ids.h"
default:
- fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
+ fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", devid);
return false;
}
assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
+ devinfo->chipset_id = devid;
return true;
}
return NULL;
}
}
+
+/**
+ * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
+ * (kernel 4.13+)
+ */
+static bool
+getparam_topology(struct gen_device_info *devinfo, int fd)
+{
+ int slice_mask = 0;
+ if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
+ return false;
+
+ int n_eus;
+ if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
+ return false;
+
+ int subslice_mask = 0;
+ if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
+ return false;
+
+ return gen_device_info_update_from_masks(devinfo,
+ slice_mask,
+ subslice_mask,
+ n_eus);
+}
+
+/**
+ * preferred API for updating the topology in devinfo (kernel 4.17+)
+ */
+static bool
+query_topology(struct gen_device_info *devinfo, int fd)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
+ };
+ struct drm_i915_query query = {
+ .num_items = 1,
+ .items_ptr = (uintptr_t) &item,
+ };
+
+ if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
+ return false;
+
+ struct drm_i915_query_topology_info *topo_info =
+ (struct drm_i915_query_topology_info *) calloc(1, item.length);
+ item.data_ptr = (uintptr_t) topo_info;
+
+ if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
+ item.length <= 0)
+ return false;
+
+ gen_device_info_update_from_topology(devinfo,
+ topo_info);
+
+ free(topo_info);
+
+ return true;
+
+}
+
+bool
+gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
+{
+ int devid = gen_get_pci_device_id_override();
+ if (devid > 0) {
+ if (!gen_get_device_info(devid, devinfo))
+ return false;
+ devinfo->no_hw = true;
+ } else {
+ /* query the device id */
+ if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
+ return false;
+ if (!gen_get_device_info(devid, devinfo))
+ return false;
+ devinfo->no_hw = false;
+ }
+
+ /* remaining initializion queries the kernel for device info */
+ if (devinfo->no_hw)
+ return true;
+
+ int timestamp_frequency;
+ if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ ×tamp_frequency))
+ devinfo->timestamp_frequency = timestamp_frequency;
+ else if (devinfo->gen >= 10)
+ /* gen10 and later requires the timestamp_frequency to be updated */
+ return false;
+
+ if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
+ return false;
+
+ if (!query_topology(devinfo, fd)) {
+ if (devinfo->gen >= 10) {
+ /* topology uAPI required for CNL+ (kernel 4.17+) */
+ return false;
+ }
+
+ /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
+ * will be wrong, affecting GPU metrics. In this case, fail silently.
+ */
+ getparam_topology(devinfo, fd);
+ }
+
+ return true;
+}
projects / mesa.git / blobdiff