iris: Implement INTEL_DEBUG=pc for pipe control logging.

[mesa.git] / src / intel / dev / gen_device_info.c

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 7c9b986f064b1f43cb1933cf965cdbe6d177ed60..fec6159fd374fc07b72201a3513a919006552756 100644 (file)
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -61,6 +61,7 @@ gen_device_name_to_pci_device_id(const char *name)
       { "glk", 0x3185 },
       { "cfl", 0x3E9B },
       { "whl", 0x3EA1 },
+      { "cml", 0x9b41 },
       { "cnl", 0x5a52 },
       { "icl", 0x8a52 },
    };
@@ -414,6 +415,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
    .has_64bit_types = true,                         \
    .supports_simd16_3src = true,                    \
    .has_surface_tile_offset = true,                 \
+   .num_thread_per_eu = 7,                          \
    .max_vs_threads = 504,                           \
    .max_tcs_threads = 504,                          \
    .max_tes_threads = 504,                          \
@@ -427,7 +429,6 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = {
    .num_slices = 1,
    .num_subslices = { 2, },
    .num_eu_per_subslice = 8,
-   .num_thread_per_eu = 7,
    .l3_banks = 2,
    .max_cs_threads = 42,
    .urb = {
@@ -452,7 +453,6 @@ static const struct gen_device_info gen_device_info_bdw_gt2 = {
    .num_slices = 1,
    .num_subslices = { 3, },
    .num_eu_per_subslice = 8,
-   .num_thread_per_eu = 7,
    .l3_banks = 4,
    .max_cs_threads = 56,
    .urb = {
@@ -477,7 +477,6 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = {
    .num_slices = 2,
    .num_subslices = { 3, 3, },
    .num_eu_per_subslice = 8,
-   .num_thread_per_eu = 7,
    .l3_banks = 8,
    .max_cs_threads = 56,
    .urb = {
@@ -503,7 +502,6 @@ static const struct gen_device_info gen_device_info_chv = {
    .num_slices = 1,
    .num_subslices = { 2, },
    .num_eu_per_subslice = 8,
-   .num_thread_per_eu = 7,
    .l3_banks = 2,
    .max_vs_threads = 80,
    .max_tcs_threads = 80,
@@ -609,8 +607,7 @@ static const struct gen_device_info gen_device_info_chv = {
 #define GEN9_FEATURES                               \
    GEN8_FEATURES,                                   \
    GEN9_HW_INFO,                                    \
-   .has_sample_with_hiz = true,                     \
-   .num_thread_per_eu = 7
+   .has_sample_with_hiz = true
 
 static const struct gen_device_info gen_device_info_skl_gt1 = {
    GEN9_FEATURES, .gt = 1,
@@ -620,6 +617,10 @@ static const struct gen_device_info gen_device_info_skl_gt1 = {
    .num_eu_per_subslice = 6,
    .l3_banks = 2,
    .urb.size = 192,
+   /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+    * leading to some vertices to go missing if we use too much URB.
+    */
+   .urb.max_entries[MESA_SHADER_VERTEX] = 928,
    .simulator_id = 12,
 };
 
@@ -691,6 +692,10 @@ static const struct gen_device_info gen_device_info_kbl_gt1 = {
    .num_subslices = { 2, },
    .num_eu_per_subslice = 6,
    .l3_banks = 2,
+   /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+    * leading to some vertices to go missing if we use too much URB.
+    */
+   .urb.max_entries[MESA_SHADER_VERTEX] = 928,
    .simulator_id = 16,
 };
 
@@ -778,6 +783,10 @@ static const struct gen_device_info gen_device_info_cfl_gt1 = {
    .num_eu_per_subslice = 6,
    .l3_banks = 2,
    .urb.size = 192,
+   /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
+    * leading to some vertices to go missing if we use too much URB.
+    */
+   .urb.max_entries[MESA_SHADER_VERTEX] = 928,
    .simulator_id = 24,
 };
 static const struct gen_device_info gen_device_info_cfl_gt2 = {
@@ -934,6 +943,66 @@ static const struct gen_device_info gen_device_info_icl_1x8 = {
    .simulator_id = 19,
 };
 
+static const struct gen_device_info gen_device_info_ehl_4x8 = {
+   GEN11_FEATURES(1, 1, subslices(4), 4),
+   .urb = {
+      .size = 512,
+      .min_entries = {
+         [MESA_SHADER_VERTEX]    = 64,
+         [MESA_SHADER_TESS_EVAL] = 34,
+      },
+      .max_entries = {
+         [MESA_SHADER_VERTEX]    = 2384,
+         [MESA_SHADER_TESS_CTRL] = 1032,
+         [MESA_SHADER_TESS_EVAL] = 2384,
+         [MESA_SHADER_GEOMETRY]  = 1032,
+      },
+   },
+   .simulator_id = 28,
+};
+
+/* FIXME: Verfiy below entries when more information is available for this SKU.
+ */
+static const struct gen_device_info gen_device_info_ehl_4x4 = {
+   GEN11_FEATURES(1, 1, subslices(4), 4),
+   .urb = {
+      .size = 512,
+      .min_entries = {
+         [MESA_SHADER_VERTEX]    = 64,
+         [MESA_SHADER_TESS_EVAL] = 34,
+      },
+      .max_entries = {
+         [MESA_SHADER_VERTEX]    = 2384,
+         [MESA_SHADER_TESS_CTRL] = 1032,
+         [MESA_SHADER_TESS_EVAL] = 2384,
+         [MESA_SHADER_GEOMETRY]  = 1032,
+      },
+   },
+   .num_eu_per_subslice = 4,
+   .simulator_id = 28,
+};
+
+/* FIXME: Verfiy below entries when more information is available for this SKU.
+ */
+static const struct gen_device_info gen_device_info_ehl_2x4 = {
+   GEN11_FEATURES(1, 1, subslices(2), 4),
+   .urb = {
+      .size = 512,
+      .min_entries = {
+         [MESA_SHADER_VERTEX]    = 64,
+         [MESA_SHADER_TESS_EVAL] = 34,
+      },
+      .max_entries = {
+         [MESA_SHADER_VERTEX]    = 2384,
+         [MESA_SHADER_TESS_CTRL] = 1032,
+         [MESA_SHADER_TESS_EVAL] = 2384,
+         [MESA_SHADER_GEOMETRY]  = 1032,
+      },
+   },
+   .num_eu_per_subslice =4,
+   .simulator_id = 28,
+};
+
 static void
 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
                             unsigned slice,
@@ -1114,7 +1183,7 @@ gen_get_device_info(int devid, struct gen_device_info *devinfo)
       case id: *devinfo = gen_device_info_##family; break;
 #include "pci_ids/i965_pci_ids.h"
    default:
-      fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
+      fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", devid);
       return false;
    }