bool has_surface_tile_offset;
bool supports_simd16_3src;
bool has_resource_streamer;
+ bool disable_ccs_repack;
/**
* \name Intel hardware quirks
*/
int simulator_id;
+ /**
+ * holds the pci device id
+ */
+ uint32_t chipset_id;
+
+ /**
+ * no_hw is true when the chipset_id pci device id has been overridden
+ */
+ bool no_hw;
/** @} */
};
const char *gen_get_device_name(int devid);
/* Used with SLICE_MASK/SUBSLICE_MASK values from DRM_I915_GETPARAM. */
-void gen_device_info_update_from_masks(struct gen_device_info *devinfo,
+bool gen_device_info_update_from_masks(struct gen_device_info *devinfo,
uint32_t slice_mask,
uint32_t subslice_mask,
uint32_t n_eus);
void gen_device_info_update_from_topology(struct gen_device_info *devinfo,
const struct drm_i915_query_topology_info *topology);
+static inline uint64_t
+gen_device_info_timebase_scale(const struct gen_device_info *devinfo,
+ uint64_t gpu_timestamp)
+{
+ return (1000000000ull * gpu_timestamp) / devinfo->timestamp_frequency;
+}
+
+bool gen_get_device_info_from_fd(int fh, struct gen_device_info *devinfo);
+
#ifdef __cplusplus
}
#endif