intel: genxml: decode variable length MI_LRI

[mesa.git] / src / intel / genxml / gen5.xml

diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 650692f6bda5d448fa775cb917d7b0a531c0baf5..5c93ecdda30fac0c1d3321deba8cc8efd902f6bf 100644 (file)
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -974,6 +974,10 @@
     <field name="DWord Length" start="0" end="5" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="63" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="31" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_STORE_DATA_IMM" bias="2" length="5">