intel/genxml: Normalize URB Data field in WM_STATE.

[mesa.git] / src / intel / genxml / gen5.xml

diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index d6b266229dd2efbafb60856fa01a033418f51e3d..44dd0d10aa3606b7363dc2fc848675f7dfe551de 100644 (file)
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -893,13 +893,13 @@
     <field name="Constant URB Entry Read Offset" start="114" end="119" type="uint"/>
     <field name="Setup URB Entry Read Length" start="107" end="112" type="uint"/>
     <field name="Setup URB Entry Read Offset" start="100" end="105" type="uint"/>
-    <field name="Dispatch GRF Start Register For URB Data" start="96" end="99" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data 0" start="96" end="99" type="uint"/>
     <field name="Sampler State Pointer" start="133" end="159" type="address"/>
     <field name="Sampler Count" start="130" end="132" type="uint"/>
     <field name="Statistics Enable" start="128" end="128" type="bool"/>
     <field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
     <field name="Legacy Diamond Line Rasterization" start="183" end="183" type="bool"/>
-    <field name="Pixel Shader Kill Pixel" start="182" end="182" type="bool"/>
+    <field name="Pixel Shader Kills Pixel" start="182" end="182" type="bool"/>
     <field name="Pixel Shader Computed Depth" start="181" end="181" type="bool"/>
     <field name="Pixel Shader Uses Source Depth" start="180" end="180" type="bool"/>
     <field name="Thread Dispatch Enable" start="179" end="179" type="bool"/>