anv/icl: Set Enabled Texel Offset Precision Fix bit

[mesa.git] / src / intel / genxml / gen9.xml

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0912b6f7fe42689946580bab4d2bd6e38f7995aa..ca268254503683649fb743853e29dad25a4cdf1a 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2868,7 +2868,7 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Stereoscopic 3D Mode" start="63" end="63" type="bool"/>
     <field name="Display Buffer Pitch" start="38" end="47" type="uint"/>
-    <field name="Tile Parameter" start="32" end="34" type="bool"/>
+    <field name="Tile Parameter" start="32" end="34" type="uint"/>
     <field name="Display Buffer Base Address" start="76" end="95" type="address"/>
     <field name="Flip Type" start="64" end="65" type="uint">
       <value name="Sync Flip" value="0"/>
@@ -2894,6 +2894,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">
@@ -2935,7 +2939,7 @@
       <value name="Display Plane 1 B" value="1"/>
       <value name="Display Plane 1 C" value="4"/>
     </field>
-    <field name="Scan Line Event Done Forward" start="17" end="18" type="bool"/>
+    <field name="Scan Line Event Done Forward" start="17" end="18" type="uint"/>
     <field name="DWord Length" start="0" end="5" type="uint" default="0"/>
     <field name="Start Scan Line Number" start="48" end="60" type="uint"/>
     <field name="End Scan Line Number" start="32" end="44" type="uint"/>
@@ -3480,7 +3484,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>
@@ -3699,6 +3703,10 @@
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="4" end="4" type="bool"/>
+
+    <field name="3D Rendering Instruction Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="20" end="20" type="bool"/>
   </register>
 
 </genxml>