#include <stdarg.h>
#include <stdio.h>
+#include "genxml/genX_bits.h"
+
#include "isl.h"
#include "isl_gen4.h"
#include "isl_gen6.h"
void
isl_device_init(struct isl_device *dev,
- const struct brw_device_info *info,
+ const struct gen_device_info *info,
bool has_bit6_swizzling)
{
dev->info = info;
assert(info->has_hiz_and_separate_stencil);
if (info->must_use_separate_stencil)
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
+
+ dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
+ dev->ss.align = isl_align(dev->ss.size, 32);
+
+ dev->ss.clear_value_size =
+ isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
+ RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
+ RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
+ RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
+
+ dev->ss.clear_value_offset =
+ RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
+
+ assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ss.addr_offset =
+ RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
+
+ /* The "Auxiliary Surface Base Address" field starts a bit higher up
+ * because the bottom 12 bits are used for other things. Round down to
+ * the nearest dword before.
+ */
+ dev->ss.aux_addr_offset =
+ (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
+
+ dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
+ assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.depth_offset =
+ _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ if (dev->use_separate_stencil) {
+ dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_CLEAR_PARAMS_length(info) * 4;
+
+ assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.stencil_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.hiz_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+ } else {
+ dev->ds.stencil_offset = 0;
+ dev->ds.hiz_offset = 0;
+ }
}
/**
/**
* @param[out] info is written only on success
*/
-bool
-isl_tiling_get_info(const struct isl_device *dev,
- enum isl_tiling tiling,
+static void
+isl_tiling_get_info(enum isl_tiling tiling,
uint32_t format_bpb,
struct isl_tile_info *tile_info)
{
const uint32_t bs = format_bpb / 8;
struct isl_extent2d logical_el, phys_B;
- assert(tiling == ISL_TILING_LINEAR || isl_is_pow2(format_bpb));
+ if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
+ /* It is possible to have non-power-of-two formats in a tiled buffer.
+ * The easiest way to handle this is to treat the tile as if it is three
+ * times as wide. This way no pixel will ever cross a tile boundary.
+ * This really only works on legacy X and Y tiling formats.
+ */
+ assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
+ assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
+ isl_tiling_get_info(tiling, format_bpb / 3, tile_info);
+ return;
+ }
switch (tiling) {
case ISL_TILING_LINEAR:
case ISL_TILING_Yf:
case ISL_TILING_Ys: {
- if (ISL_DEV_GEN(dev) < 9)
- return false;
-
- if (!isl_is_pow2(bs))
- return false;
-
bool is_Ys = tiling == ISL_TILING_Ys;
assert(bs > 0);
*tile_info = (struct isl_tile_info) {
.tiling = tiling,
+ .format_bpb = format_bpb,
.logical_extent_el = logical_el,
.phys_extent_B = phys_B,
};
+}
+
+bool
+isl_color_value_is_zero(union isl_color_value value,
+ enum isl_format format)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+#define RETURN_FALSE_IF_NOT_0(c, i) \
+ if (fmtl->channels.c.bits && value.u32[i] != 0) \
+ return false
+
+ RETURN_FALSE_IF_NOT_0(r, 0);
+ RETURN_FALSE_IF_NOT_0(g, 1);
+ RETURN_FALSE_IF_NOT_0(b, 2);
+ RETURN_FALSE_IF_NOT_0(a, 3);
+
+#undef RETURN_FALSE_IF_NOT_0
+
+ return true;
+}
+
+bool
+isl_color_value_is_zero_one(union isl_color_value value,
+ enum isl_format format)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+#define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
+ if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
+ return false
+
+ if (isl_format_has_int_channel(format)) {
+ RETURN_FALSE_IF_NOT_0_1(r, 0, u32);
+ RETURN_FALSE_IF_NOT_0_1(g, 1, u32);
+ RETURN_FALSE_IF_NOT_0_1(b, 2, u32);
+ RETURN_FALSE_IF_NOT_0_1(a, 3, u32);
+ } else {
+ RETURN_FALSE_IF_NOT_0_1(r, 0, f32);
+ RETURN_FALSE_IF_NOT_0_1(g, 1, f32);
+ RETURN_FALSE_IF_NOT_0_1(b, 2, f32);
+ RETURN_FALSE_IF_NOT_0_1(a, 3, f32);
+ }
+
+#undef RETURN_FALSE_IF_NOT_0_1
return true;
}
/**
* @param[out] tiling is set only on success
*/
-bool
+static bool
isl_surf_choose_tiling(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling *tiling)
{
isl_tiling_flags_t tiling_flags = info->tiling_flags;
- if (ISL_DEV_GEN(dev) >= 7) {
- gen7_filter_tiling(dev, info, &tiling_flags);
+ /* HiZ surfaces always use the HiZ tiling */
+ if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
+ assert(info->format == ISL_FORMAT_HIZ);
+ assert(tiling_flags == ISL_TILING_HIZ_BIT);
+ *tiling = ISL_TILING_HIZ;
+ return true;
+ }
+
+ /* CCS surfaces always use the CCS tiling */
+ if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
+ assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
+ assert(tiling_flags == ISL_TILING_CCS_BIT);
+ *tiling = ISL_TILING_CCS;
+ return true;
+ }
+
+ if (ISL_DEV_GEN(dev) >= 6) {
+ isl_gen6_filter_tiling(dev, info, &tiling_flags);
} else {
- isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
- gen7_filter_tiling(dev, info, &tiling_flags);
+ isl_gen4_filter_tiling(dev, info, &tiling_flags);
}
#define CHOOSE(__tiling) \
CHOOSE(ISL_TILING_LINEAR);
}
- CHOOSE(ISL_TILING_CCS);
- CHOOSE(ISL_TILING_HIZ);
CHOOSE(ISL_TILING_Ys);
CHOOSE(ISL_TILING_Yf);
CHOOSE(ISL_TILING_Y0);
enum isl_msaa_layout *msaa_layout)
{
if (ISL_DEV_GEN(dev) >= 8) {
- return gen8_choose_msaa_layout(dev, info, tiling, msaa_layout);
+ return isl_gen8_choose_msaa_layout(dev, info, tiling, msaa_layout);
} else if (ISL_DEV_GEN(dev) >= 7) {
- return gen7_choose_msaa_layout(dev, info, tiling, msaa_layout);
+ return isl_gen7_choose_msaa_layout(dev, info, tiling, msaa_layout);
} else if (ISL_DEV_GEN(dev) >= 6) {
- return gen6_choose_msaa_layout(dev, info, tiling, msaa_layout);
+ return isl_gen6_choose_msaa_layout(dev, info, tiling, msaa_layout);
} else {
- return gen4_choose_msaa_layout(dev, info, tiling, msaa_layout);
+ return isl_gen4_choose_msaa_layout(dev, info, tiling, msaa_layout);
}
}
-static void
-isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,
- uint32_t *width, uint32_t *height)
+struct isl_extent2d
+isl_get_interleaved_msaa_px_size_sa(uint32_t samples)
{
assert(isl_is_pow2(samples));
* MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
* proceeding: [...]
*/
+ return (struct isl_extent2d) {
+ .width = 1 << ((ffs(samples) - 0) / 2),
+ .height = 1 << ((ffs(samples) - 1) / 2),
+ };
+}
+
+static void
+isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,
+ uint32_t *width, uint32_t *height)
+{
+ const struct isl_extent2d px_size_sa =
+ isl_get_interleaved_msaa_px_size_sa(samples);
+
if (width)
- *width = isl_align(*width, 2) << ((ffs(samples) - 0) / 2);
+ *width = isl_align(*width, 2) * px_size_sa.width;
if (height)
- *height = isl_align(*height, 2) << ((ffs(samples) - 1) / 2);
+ *height = isl_align(*height, 2) * px_size_sa.height;
}
static enum isl_array_pitch_span
* the storage for LODs other than LOD 0 is not needed.
*/
assert(info->levels == 1);
- assert(phys_level0_sa->array_len == 1);
return ISL_ARRAY_PITCH_SPAN_COMPACT;
} else {
if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) &&
* compact QPitch possible in order to conserve memory.
*/
return ISL_ARRAY_PITCH_SPAN_COMPACT;
+
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ /* Each array image in the gen6 stencil of HiZ surface is compact in the
+ * sense that every LOD is a compact array of the same size as LOD0.
+ */
+ return ISL_ARRAY_PITCH_SPAN_COMPACT;
}
unreachable("bad isl_dim_layout");
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el)
{
- if (info->format == ISL_FORMAT_HIZ) {
- assert(ISL_DEV_GEN(dev) >= 6);
- /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
- * which works out to 2x2 HiZ elments.
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ if (fmtl->txc == ISL_TXC_MCS) {
+ assert(tiling == ISL_TILING_Y0);
+
+ /*
+ * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
+ *
+ * Height, width, and layout of MCS buffer in this case must match with
+ * Render Target height, width, and layout. MCS buffer is tiledY.
+ *
+ * To avoid wasting memory, choose the smallest alignment possible:
+ * HALIGN_4 and VALIGN_4.
*/
- *image_align_el = isl_extent3d(2, 2, 1);
+ *image_align_el = isl_extent3d(4, 4, 1);
+ return;
+ } else if (info->format == ISL_FORMAT_HIZ) {
+ assert(ISL_DEV_GEN(dev) >= 6);
+ if (ISL_DEV_GEN(dev) == 6) {
+ /* HiZ surfaces on Sandy Bridge are packed tightly. */
+ *image_align_el = isl_extent3d(1, 1, 1);
+ } else {
+ /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
+ * primary surface which works out to 2x2 HiZ elments.
+ */
+ *image_align_el = isl_extent3d(2, 2, 1);
+ }
return;
}
if (ISL_DEV_GEN(dev) >= 9) {
- gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
- msaa_layout, image_align_el);
+ isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 8) {
- gen8_choose_image_alignment_el(dev, info, tiling, dim_layout,
- msaa_layout, image_align_el);
+ isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 7) {
- gen7_choose_image_alignment_el(dev, info, tiling, dim_layout,
- msaa_layout, image_align_el);
+ isl_gen7_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 6) {
- gen6_choose_image_alignment_el(dev, info, tiling, dim_layout,
- msaa_layout, image_align_el);
+ isl_gen6_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else {
- gen4_choose_image_alignment_el(dev, info, tiling, dim_layout,
- msaa_layout, image_align_el);
+ isl_gen4_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
}
}
static enum isl_dim_layout
isl_surf_choose_dim_layout(const struct isl_device *dev,
enum isl_surf_dim logical_dim,
- enum isl_tiling tiling)
+ enum isl_tiling tiling,
+ isl_surf_usage_flags_t usage)
{
+ /* Sandy bridge needs a special layout for HiZ and stencil. */
+ if (ISL_DEV_GEN(dev) == 6 &&
+ (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
+ return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ;
+
if (ISL_DEV_GEN(dev) >= 9) {
switch (logical_dim) {
case ISL_SURF_DIM_1D:
switch (logical_dim) {
case ISL_SURF_DIM_1D:
case ISL_SURF_DIM_2D:
+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+ *
+ * The cube face textures are stored in the same way as 3D surfaces
+ * are stored (see section 6.17.5 for details). For cube surfaces,
+ * however, the depth is equal to the number of faces (always 6) and
+ * is not reduced for each MIP.
+ */
+ if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
+ return ISL_DIM_LAYOUT_GEN4_3D;
+
return ISL_DIM_LAYOUT_GEN4_2D;
case ISL_SURF_DIM_3D:
return ISL_DIM_LAYOUT_GEN4_3D;
assert(info->height == 1);
assert(info->depth == 1);
assert(info->samples == 1);
- assert(!isl_format_is_compressed(info->format));
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN4_3D:
case ISL_DIM_LAYOUT_GEN9_1D:
case ISL_DIM_LAYOUT_GEN4_2D:
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
*phys_level0_sa = (struct isl_extent4d) {
- .w = info->width,
- .h = 1,
+ .w = isl_align_npot(info->width, fmtl->bw),
+ .h = fmtl->bh,
.d = 1,
.a = info->array_len,
};
break;
case ISL_SURF_DIM_2D:
- assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D);
+ if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
+ else
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
+ dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
if (tiling == ISL_TILING_Ys && info->samples > 1)
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
case ISL_MSAA_LAYOUT_ARRAY:
assert(info->depth == 1);
- assert(info->array_len == 1);
- assert(!isl_format_is_compressed(info->format));
+ assert(info->levels == 1);
+ assert(isl_format_supports_multisampling(dev->info, info->format));
+ assert(fmtl->bw == 1 && fmtl->bh == 1);
*phys_level0_sa = (struct isl_extent4d) {
.w = info->width,
.h = info->height,
.d = 1,
- .a = info->samples,
+ .a = info->array_len * info->samples,
};
break;
case ISL_MSAA_LAYOUT_INTERLEAVED:
assert(info->depth == 1);
- assert(info->array_len == 1);
- assert(!isl_format_is_compressed(info->format));
+ assert(info->levels == 1);
+ assert(isl_format_supports_multisampling(dev->info, info->format));
*phys_level0_sa = (struct isl_extent4d) {
.w = info->width,
.h = info->height,
.d = 1,
- .a = 1,
+ .a = info->array_len,
};
isl_msaa_interleaved_scale_px_to_sa(info->samples,
&phys_level0_sa->w,
&phys_level0_sa->h);
+
+ phys_level0_sa->w = isl_align(phys_level0_sa->w, fmtl->bw);
+ phys_level0_sa->h = isl_align(phys_level0_sa->h, fmtl->bh);
break;
}
break;
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN4_2D:
}
}
+/**
+ * Calculate the pitch between physical array slices, in units of rows of
+ * surface elements.
+ */
+static uint32_t
+isl_calc_array_pitch_el_rows_gen4_2d(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ const struct isl_extent2d *phys_slice0_sa)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ uint32_t pitch_sa_rows = 0;
+
+ switch (array_pitch_span) {
+ case ISL_ARRAY_PITCH_SPAN_COMPACT:
+ pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
+ break;
+ case ISL_ARRAY_PITCH_SPAN_FULL: {
+ /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
+ * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
+ * Surfaces >> Surface Arrays.
+ */
+ uint32_t H0_sa = phys_level0_sa->h;
+ uint32_t H1_sa = isl_minify(H0_sa, 1);
+
+ uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
+ uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
+
+ uint32_t m;
+ if (ISL_DEV_GEN(dev) >= 7) {
+ /* The QPitch equation changed slightly in Ivybridge. */
+ m = 12;
+ } else {
+ m = 11;
+ }
+
+ pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
+
+ if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
+ (info->height % 4 == 1)) {
+ /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
+ * Graphics Core >> Section 7.18.3.7: Surface Arrays:
+ *
+ * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
+ * the value calculated in the equation above , for every
+ * other odd Surface Height starting from 1 i.e. 1,5,9,13.
+ *
+ * XXX(chadv): Is the errata natural corollary of the physical
+ * layout of interleaved samples?
+ */
+ pitch_sa_rows += 4;
+ }
+
+ pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
+ } /* end case */
+ break;
+ }
+
+ assert(pitch_sa_rows % fmtl->bh == 0);
+ uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
+
+ if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
+ /*
+ * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
+ *
+ * "Mip-mapped and arrayed surfaces are supported with MCS buffer
+ * layout with these alignments in the RT space: Horizontal
+ * Alignment = 128 and Vertical Alignment = 64."
+ *
+ * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
+ *
+ * "For non-multisampled render target's CCS auxiliary surface,
+ * QPitch must be computed with Horizontal Alignment = 128 and
+ * Surface Vertical Alignment = 256. These alignments are only for
+ * CCS buffer and not for associated render target."
+ *
+ * The first restriction is already handled by isl_choose_image_alignment_el
+ * but the second restriction, which is an extension of the first, only
+ * applies to qpitch and must be applied here.
+ */
+ assert(fmtl->bh == 4);
+ pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
+ }
+
+ if (ISL_DEV_GEN(dev) >= 9 &&
+ info->dim == ISL_SURF_DIM_3D &&
+ tile_info->tiling != ISL_TILING_LINEAR) {
+ /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
+ *
+ * Tile Mode != Linear: This field must be set to an integer multiple
+ * of the tile height
+ */
+ pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
+ }
+
+ return pitch_el_rows;
+}
+
/**
* A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_2D.
};
}
+static void
+isl_calc_phys_total_extent_el_gen4_2d(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ enum isl_msaa_layout msaa_layout,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *total_extent_el)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
+ struct isl_extent2d phys_slice0_sa;
+ isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout,
+ image_align_sa, phys_level0_sa,
+ &phys_slice0_sa);
+ *array_pitch_el_rows =
+ isl_calc_array_pitch_el_rows_gen4_2d(dev, info, tile_info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_span,
+ &phys_slice0_sa);
+ *total_extent_el = (struct isl_extent2d) {
+ .w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
+ .h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
+ isl_assert_div(phys_slice0_sa.h, fmtl->bh),
+ };
+}
+
/**
* A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_3D.
*/
static void
-isl_calc_phys_slice0_extent_sa_gen4_3d(
+isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
assert(info->samples == 1);
- assert(phys_level0_sa->array_len == 1);
- uint32_t slice_w = 0;
- uint32_t slice_h = 0;
+ if (info->dim != ISL_SURF_DIM_3D) {
+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+ *
+ * The cube face textures are stored in the same way as 3D surfaces
+ * are stored (see section 6.17.5 for details). For cube surfaces,
+ * however, the depth is equal to the number of faces (always 6) and
+ * is not reduced for each MIP.
+ */
+ assert(ISL_DEV_GEN(dev) == 4);
+ assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
+ assert(phys_level0_sa->array_len == 6);
+ } else {
+ assert(phys_level0_sa->array_len == 1);
+ }
+
+ uint32_t total_w = 0;
+ uint32_t total_h = 0;
uint32_t W0 = phys_level0_sa->w;
uint32_t H0 = phys_level0_sa->h;
uint32_t D0 = phys_level0_sa->d;
+ uint32_t A0 = phys_level0_sa->a;
for (uint32_t l = 0; l < info->levels; ++l) {
uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);
uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
- uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d);
+ uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;
uint32_t max_layers_horiz = MIN(level_d, 1u << l);
uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
- slice_w = MAX(slice_w, level_w * max_layers_horiz);
- slice_h += level_h * max_layers_vert;
+ total_w = MAX(total_w, level_w * max_layers_horiz);
+ total_h += level_h * max_layers_vert;
}
- *phys_slice0_sa = (struct isl_extent2d) {
- .w = slice_w,
- .h = slice_h,
+ /* GEN4_3D layouts don't really have an array pitch since each LOD has a
+ * different number of horizontal and vertical layers. We have to set it
+ * to something, so at least make it true for LOD0.
+ */
+ *array_pitch_el_rows =
+ isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(total_w, fmtl->bw),
+ .h = isl_assert_div(total_h, fmtl->bh),
+ };
+}
+
+/**
+ * A variant of isl_calc_phys_slice0_extent_sa() specific to
+ * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
+ */
+static void
+isl_calc_phys_total_extent_el_gen6_stencil_hiz(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
+ const struct isl_extent2d tile_extent_sa = {
+ .w = tile_info->logical_extent_el.w * fmtl->bw,
+ .h = tile_info->logical_extent_el.h * fmtl->bh,
+ };
+ /* Tile size is a multiple of image alignment */
+ assert(tile_extent_sa.w % image_align_sa->w == 0);
+ assert(tile_extent_sa.h % image_align_sa->h == 0);
+
+ const uint32_t W0 = phys_level0_sa->w;
+ const uint32_t H0 = phys_level0_sa->h;
+
+ /* Each image has the same height as LOD0 because the hardware thinks
+ * everything is LOD0
+ */
+ const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a;
+
+ uint32_t total_top_w = 0;
+ uint32_t total_bottom_w = 0;
+ uint32_t total_h = 0;
+
+ for (uint32_t l = 0; l < info->levels; ++l) {
+ const uint32_t W = isl_minify(W0, l);
+
+ const uint32_t w = isl_align(W, tile_extent_sa.w);
+ const uint32_t h = isl_align(H, tile_extent_sa.h);
+
+ if (l == 0) {
+ total_top_w = w;
+ total_h = h;
+ } else if (l == 1) {
+ total_bottom_w = w;
+ total_h += h;
+ } else {
+ total_bottom_w += w;
+ }
+ }
+
+ *array_pitch_el_rows =
+ isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
+ .h = isl_assert_div(total_h, fmtl->bh),
};
}
* ISL_DIM_LAYOUT_GEN9_1D.
*/
static void
-isl_calc_phys_slice0_extent_sa_gen9_1d(
+isl_calc_phys_total_extent_el_gen9_1d(
const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
{
MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
- assert(phys_level0_sa->height == 1);
+ assert(phys_level0_sa->height / fmtl->bh == 1);
assert(phys_level0_sa->depth == 1);
assert(info->samples == 1);
assert(image_align_sa->w >= fmtl->bw);
slice_w += w;
}
- *phys_slice0_sa = isl_extent2d(slice_w, 1);
+ *array_pitch_el_rows = 1;
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(slice_w, fmtl->bw),
+ .h = phys_level0_sa->array_len,
+ };
}
/**
- * Calculate the physical extent of the surface's first array slice, in units
- * of surface samples. If the surface is multi-leveled, then the result will
- * be aligned to \a image_align_sa.
+ * Calculate the two-dimensional total physical extent of the surface, in
+ * units of surface elements.
*/
static void
-isl_calc_phys_slice0_extent_sa(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- enum isl_dim_layout dim_layout,
- enum isl_msaa_layout msaa_layout,
- const struct isl_extent3d *image_align_sa,
- const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+isl_calc_phys_total_extent_el(const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ enum isl_dim_layout dim_layout,
+ enum isl_msaa_layout msaa_layout,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *total_extent_el)
{
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
- isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info,
- image_align_sa, phys_level0_sa,
- phys_slice0_sa);
+ assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+ isl_calc_phys_total_extent_el_gen9_1d(dev, info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
return;
case ISL_DIM_LAYOUT_GEN4_2D:
- isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout,
- image_align_sa, phys_level0_sa,
- phys_slice0_sa);
+ isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout,
+ image_align_sa, phys_level0_sa,
+ array_pitch_span,
+ array_pitch_el_rows,
+ total_extent_el);
+ return;
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+ isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev, info, tile_info,
+ image_align_sa,
+ phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
return;
case ISL_DIM_LAYOUT_GEN4_3D:
- isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa,
- phys_level0_sa, phys_slice0_sa);
+ assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+ isl_calc_phys_total_extent_el_gen4_3d(dev, info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
return;
}
}
-/**
- * Calculate the pitch between physical array slices, in units of rows of
- * surface elements.
- */
static uint32_t
-isl_calc_array_pitch_el_rows(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- const struct isl_tile_info *tile_info,
- enum isl_dim_layout dim_layout,
- enum isl_array_pitch_span array_pitch_span,
- const struct isl_extent3d *image_align_sa,
- const struct isl_extent4d *phys_level0_sa,
- const struct isl_extent2d *phys_slice0_sa)
+isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info)
{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
- uint32_t pitch_sa_rows = 0;
+ if (tile_info->tiling != ISL_TILING_LINEAR)
+ return tile_info->phys_extent_B.width;
- switch (dim_layout) {
- case ISL_DIM_LAYOUT_GEN9_1D:
- /* Each row is an array slice */
- pitch_sa_rows = 1;
- break;
- case ISL_DIM_LAYOUT_GEN4_2D:
- switch (array_pitch_span) {
- case ISL_ARRAY_PITCH_SPAN_COMPACT:
- pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
- break;
- case ISL_ARRAY_PITCH_SPAN_FULL: {
- /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
- * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
- * Surfaces >> Surface Arrays.
- */
- uint32_t H0_sa = phys_level0_sa->h;
- uint32_t H1_sa = isl_minify(H0_sa, 1);
+ /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
+ * RENDER_SURFACE_STATE Surface Pitch (p349):
+ *
+ * - For linear render target surfaces and surfaces accessed with the
+ * typed data port messages, the pitch must be a multiple of the
+ * element size for non-YUV surface formats. Pitch must be
+ * a multiple of 2 * element size for YUV surface formats.
+ *
+ * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
+ * ignore because isl doesn't do buffers.]
+ *
+ * - For other linear surfaces, the pitch can be any multiple of
+ * bytes.
+ */
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
+ const uint32_t bs = fmtl->bpb / 8;
- uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
- uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
+ if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
+ if (isl_format_is_yuv(surf_info->format)) {
+ return 2 * bs;
+ } else {
+ return bs;
+ }
+ }
- uint32_t m;
- if (ISL_DEV_GEN(dev) >= 7) {
- /* The QPitch equation changed slightly in Ivybridge. */
- m = 12;
- } else {
- m = 11;
- }
+ return 1;
+}
- pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
+static uint32_t
+isl_calc_linear_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *info,
+ const struct isl_extent2d *phys_total_el,
+ uint32_t alignment)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ const uint32_t bs = fmtl->bpb / 8;
- if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
- (info->height % 4 == 1)) {
- /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
- * Graphics Core >> Section 7.18.3.7: Surface Arrays:
- *
- * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
- * the value calculated in the equation above , for every
- * other odd Surface Height starting from 1 i.e. 1,5,9,13.
- *
- * XXX(chadv): Is the errata natural corollary of the physical
- * layout of interleaved samples?
- */
- pitch_sa_rows += 4;
- }
-
- pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
- } /* end case */
- break;
- }
- break;
- case ISL_DIM_LAYOUT_GEN4_3D:
- assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
- pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
- break;
- default:
- unreachable("bad isl_dim_layout");
- break;
- }
+ return isl_align_npot(bs * phys_total_el->w, alignment);
+}
- assert(pitch_sa_rows % fmtl->bh == 0);
- uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
+static uint32_t
+isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent2d *phys_total_el,
+ uint32_t alignment)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
- if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
- /*
- * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
- *
- * "Mip-mapped and arrayed surfaces are supported with MCS buffer
- * layout with these alignments in the RT space: Horizontal
- * Alignment = 128 and Vertical Alignment = 64."
- *
- * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
- *
- * "For non-multisampled render target's CCS auxiliary surface,
- * QPitch must be computed with Horizontal Alignment = 128 and
- * Surface Vertical Alignment = 256. These alignments are only for
- * CCS buffer and not for associated render target."
- *
- * The first restriction is already handled by isl_choose_image_alignment_el
- * but the second restriction, which is an extension of the first, only
- * applies to qpitch and must be applied here.
- */
- assert(fmtl->bh == 4);
- pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
- }
+ assert(fmtl->bpb % tile_info->format_bpb == 0);
- if (ISL_DEV_GEN(dev) >= 9 &&
- info->dim == ISL_SURF_DIM_3D &&
- tile_info->tiling != ISL_TILING_LINEAR) {
- /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
- *
- * Tile Mode != Linear: This field must be set to an integer multiple
- * of the tile height
- */
- pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
- }
+ const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
+ const uint32_t total_w_tl =
+ isl_align_div(phys_total_el->w * tile_el_scale,
+ tile_info->logical_extent_el.width);
- return pitch_el_rows;
+ assert(alignment == tile_info->phys_extent_B.width);
+ return total_w_tl * tile_info->phys_extent_B.width;
}
-/**
- * Calculate the pitch of each surface row, in bytes.
- */
static uint32_t
-isl_calc_linear_row_pitch(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- const struct isl_extent2d *phys_slice0_sa)
+isl_calc_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent2d *phys_total_el,
+ uint32_t alignment)
{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
- uint32_t row_pitch = info->min_pitch;
-
- /* First, align the surface to a cache line boundary, as the PRM explains
- * below.
- *
- * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Render Target and Media
- * Surfaces:
- *
- * The data port accesses data (pixels) outside of the surface if they
- * are contained in the same cache request as pixels that are within the
- * surface. These pixels will not be returned by the requesting message,
- * however if these pixels lie outside of defined pages in the GTT,
- * a GTT error will result when the cache request is processed. In order
- * to avoid these GTT errors, “padding” at the bottom of the surface is
- * sometimes necessary.
- *
- * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
- *
- * The sampling engine accesses texels outside of the surface if they
- * are contained in the same cache line as texels that are within the
- * surface. These texels will not participate in any calculation
- * performed by the sampling engine and will not affect the result of
- * any sampling engine operation, however if these texels lie outside of
- * defined pages in the GTT, a GTT error will result when the cache line
- * is accessed. In order to avoid these GTT errors, “padding” at the
- * bottom and right side of a sampling engine surface is sometimes
- * necessary.
- *
- * It is possible that a cache line will straddle a page boundary if the
- * base address or pitch is not aligned. All pages included in the cache
- * lines that are part of the surface must map to valid GTT entries to
- * avoid errors. To determine the necessary padding on the bottom and
- * right side of the surface, refer to the table in Alignment Unit Size
- * section for the i and j parameters for the surface format in use. The
- * surface must then be extended to the next multiple of the alignment
- * unit size in each dimension, and all texels contained in this
- * extended surface must have valid GTT entries.
- *
- * For example, suppose the surface size is 15 texels by 10 texels and
- * the alignment parameters are i=4 and j=2. In this case, the extended
- * surface would be 16 by 10. Note that these calculations are done in
- * texels, and must be converted to bytes based on the surface format
- * being used to determine whether additional pages need to be defined.
- */
- assert(phys_slice0_sa->w % fmtl->bw == 0);
- const uint32_t bs = fmtl->bpb / 8;
- row_pitch = MAX(row_pitch, bs * (phys_slice0_sa->w / fmtl->bw));
-
- /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
- * RENDER_SURFACE_STATE Surface Pitch (p349):
- *
- * - For linear render target surfaces and surfaces accessed with the
- * typed data port messages, the pitch must be a multiple of the
- * element size for non-YUV surface formats. Pitch must be
- * a multiple of 2 * element size for YUV surface formats.
- *
- * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
- * ignore because isl doesn't do buffers.]
- *
- * - For other linear surfaces, the pitch can be any multiple of
- * bytes.
- */
- if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
- if (isl_format_is_yuv(info->format)) {
- row_pitch = isl_align_npot(row_pitch, 2 * bs);
- } else {
- row_pitch = isl_align_npot(row_pitch, bs);
- }
+ if (tile_info->tiling == ISL_TILING_LINEAR) {
+ return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
+ alignment);
+ } else {
+ return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
+ phys_total_el, alignment);
}
-
- return row_pitch;
}
/**
- * Calculate and apply any padding required for the surface.
+ * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
+ * size is `bits` bits?
*
- * @param[inout] total_h_el is updated with the new height
- * @param[out] pad_bytes is overwritten with additional padding requirements.
+ * Hardware pitch fields are offset by 1. For example, if the size of
+ * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
+ * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
+ * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
*/
-static void
-isl_apply_surface_padding(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- const struct isl_tile_info *tile_info,
- uint32_t *total_h_el,
- uint32_t *pad_bytes)
+static bool
+pitch_in_range(uint32_t n, uint32_t bits)
{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ assert(n != 0);
+ return likely(bits != 0 && 1 <= n && n <= (1 << bits));
+}
- *pad_bytes = 0;
+static bool
+isl_calc_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ enum isl_dim_layout dim_layout,
+ const struct isl_extent2d *phys_total_el,
+ uint32_t *out_row_pitch)
+{
+ uint32_t alignment =
+ isl_calc_row_pitch_alignment(surf_info, tile_info);
- /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Render Target and Media
- * Surfaces:
- *
- * The data port accesses data (pixels) outside of the surface if they
- * are contained in the same cache request as pixels that are within the
- * surface. These pixels will not be returned by the requesting message,
- * however if these pixels lie outside of defined pages in the GTT,
- * a GTT error will result when the cache request is processed. In
- * order to avoid these GTT errors, “padding” at the bottom of the
- * surface is sometimes necessary.
- *
- * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
- *
- * ... Lots of padding requirements, all listed separately below.
+ /* If pitch isn't given and it can be chosen freely, align it by cache line
+ * allowing one to use blit engine on the surface.
*/
+ if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) {
+ /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
+ *
+ * "Base address of the destination surface: X=0, Y=0. Lower 32bits
+ * of the 48bit addressing. When Src Tiling is enabled (Bit_15
+ * enabled), this address must be 4KB-aligned. When Tiling is not
+ * enabled, this address should be CL (64byte) aligned."
+ */
+ alignment = MAX2(alignment, 64);
+ }
- /* We can safely ignore the first padding requirement, quoted below,
- * because isl doesn't do buffers.
- *
- * - [pre-BDW] For buffers, which have no inherent “height,” padding
- * requirements are different. A buffer must be padded to the next
- * multiple of 256 array elements, with an additional 16 bytes added
- * beyond that to account for the L1 cache line.
- */
+ const uint32_t min_row_pitch =
+ isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
+ alignment);
- /*
- * - For compressed textures [...], padding at the bottom of the surface
- * is to an even compressed row.
- */
- if (isl_format_is_compressed(info->format))
- *total_h_el = isl_align(*total_h_el, 2);
+ uint32_t row_pitch = min_row_pitch;
- /*
- * - For cube surfaces, an additional two rows of padding are required
- * at the bottom of the surface.
- */
- if (info->usage & ISL_SURF_USAGE_CUBE_BIT)
- *total_h_el += 2;
-
- /*
- * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
- * additional padding is required. These surfaces require an extra row
- * plus 16 bytes of padding at the bottom in addition to the general
- * padding requirements.
- */
- if (isl_format_is_yuv(info->format) &&
- (fmtl->bpb == 96 || fmtl->bpb == 48|| fmtl->bpb == 24)) {
- *total_h_el += 1;
- *pad_bytes += 16;
+ if (surf_info->row_pitch != 0) {
+ row_pitch = surf_info->row_pitch;
+
+ if (row_pitch < min_row_pitch)
+ return false;
+
+ if (row_pitch % alignment != 0)
+ return false;
}
- /*
- * - For linear surfaces, additional padding of 64 bytes is required at
- * the bottom of the surface. This is in addition to the padding
- * required above.
- */
- if (tile_info->tiling == ISL_TILING_LINEAR)
- *pad_bytes += 64;
+ const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width;
- /* The below text weakens, not strengthens, the padding requirements for
- * linear surfaces. Therefore we can safely ignore it.
- *
- * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
- * non-MSAA, non-mip-mapped surfaces in linear memory, the only
- * padding requirement is to the next aligned 64-byte boundary beyond
- * the end of the surface. The rest of the padding requirements
- * documented above do not apply to these surfaces.
- */
+ if (row_pitch == 0)
+ return false;
- /*
- * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
- * height % 4 != 0, the surface must be padded with
- * 4-(height % 4)*Surface Pitch # of bytes.
- */
- if (ISL_DEV_GEN(dev) >= 9 &&
- tile_info->tiling == ISL_TILING_LINEAR &&
- (info->dim == ISL_SURF_DIM_2D || info->dim == ISL_SURF_DIM_3D)) {
- *total_h_el = isl_align(*total_h_el, 4);
+ if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
+ /* SurfacePitch is ignored for this layout. */
+ goto done;
}
- /*
- * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
- * to 4 times the Surface Pitch # of bytes
- */
- if (ISL_DEV_GEN(dev) >= 9 &&
- tile_info->tiling == ISL_TILING_LINEAR &&
- info->dim == ISL_SURF_DIM_1D) {
- *total_h_el += 4;
- }
+ if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_STORAGE_BIT)) &&
+ !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
+ ISL_SURF_USAGE_MCS_BIT)) &&
+ !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
+ _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
+ _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
+
+ if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
+ !pitch_in_range(row_pitch, stencil_pitch_bits))
+ return false;
+
+ done:
+ *out_row_pitch = row_pitch;
+ return true;
}
bool
return false;
struct isl_tile_info tile_info;
- if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, &tile_info))
- return false;
+ isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
const enum isl_dim_layout dim_layout =
- isl_surf_choose_dim_layout(dev, info->dim, tiling);
+ isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
enum isl_msaa_layout msaa_layout;
if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
enum isl_array_pitch_span array_pitch_span =
isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
- struct isl_extent2d phys_slice0_sa;
- isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout,
- &image_align_sa, &phys_level0_sa,
- &phys_slice0_sa);
- assert(phys_slice0_sa.w % fmtl->bw == 0);
- assert(phys_slice0_sa.h % fmtl->bh == 0);
-
- const uint32_t array_pitch_el_rows =
- isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout,
- array_pitch_span, &image_align_sa,
- &phys_level0_sa, &phys_slice0_sa);
-
- uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
-
- uint32_t pad_bytes;
- isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes);
+ uint32_t array_pitch_el_rows;
+ struct isl_extent2d phys_total_el;
+ isl_calc_phys_total_extent_el(dev, info, &tile_info,
+ dim_layout, msaa_layout,
+ &image_align_sa, &phys_level0_sa,
+ array_pitch_span, &array_pitch_el_rows,
+ &phys_total_el);
+
+ uint32_t row_pitch;
+ if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
+ &phys_total_el, &row_pitch))
+ return false;
- uint32_t row_pitch, size, base_alignment;
+ uint32_t base_alignment;
+ uint64_t size;
if (tiling == ISL_TILING_LINEAR) {
- row_pitch = isl_calc_linear_row_pitch(dev, info, &phys_slice0_sa);
- size = row_pitch * total_h_el + pad_bytes;
+ size = (uint64_t) row_pitch * phys_total_el.h;
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
*
base_alignment = MAX(base_alignment, fmtl->bpb / 8);
}
}
+ base_alignment = isl_round_up_to_power_of_two(base_alignment);
} else {
- assert(phys_slice0_sa.w % fmtl->bw == 0);
- const uint32_t total_w_el = phys_slice0_sa.width / fmtl->bw;
- const uint32_t total_w_tl =
- isl_align_div(total_w_el, tile_info.logical_extent_el.width);
-
- row_pitch = total_w_tl * tile_info.phys_extent_B.width;
- if (row_pitch < info->min_pitch) {
- row_pitch = isl_align(info->min_pitch, tile_info.phys_extent_B.width);
- }
-
- total_h_el += isl_align_div_npot(pad_bytes, row_pitch);
const uint32_t total_h_tl =
- isl_align_div(total_h_el, tile_info.logical_extent_el.height);
+ isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);
- size = total_h_tl * tile_info.phys_extent_B.height * row_pitch;
+ size = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch;
const uint32_t tile_size = tile_info.phys_extent_B.width *
tile_info.phys_extent_B.height;
base_alignment = MAX(info->min_alignment, tile_size);
}
+ if (ISL_DEV_GEN(dev) < 9) {
+ /* From the Broadwell PRM Vol 5, Surface Layout:
+ *
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size in bytes. This
+ * maximum is 2 GB for all products and all surface types."
+ *
+ * This comment is applicable to all Pre-gen9 platforms.
+ */
+ if (size > (uint64_t) 1 << 31)
+ return false;
+ } else if (ISL_DEV_GEN(dev) < 11) {
+ /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size of 2^38 bytes.
+ * All pixels within the surface must be contained within 2^38 bytes
+ * of the base address."
+ */
+ if (size > (uint64_t) 1 << 38)
+ return false;
+ } else {
+ /* gen11+ platforms raised this limit to 2^44 bytes. */
+ if (size > (uint64_t) 1 << 44)
+ return false;
+ }
+
*surf = (struct isl_surf) {
.dim = info->dim,
.dim_layout = dim_layout,
}
void
-isl_surf_get_tile_info(const struct isl_device *dev,
- const struct isl_surf *surf,
+isl_surf_get_tile_info(const struct isl_surf *surf,
struct isl_tile_info *tile_info)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info);
+ isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info);
}
-void
+bool
isl_surf_get_hiz_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *hiz_surf)
assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
- isl_surf_init(dev, hiz_surf,
- .dim = ISL_SURF_DIM_2D,
- .format = ISL_FORMAT_HIZ,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = 1,
- .levels = surf->levels,
- .array_len = surf->logical_level0_px.array_len,
- /* On SKL+, HiZ is always single-sampled */
- .samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples,
- .usage = ISL_SURF_USAGE_HIZ_BIT,
- .tiling_flags = ISL_TILING_HIZ_BIT);
+ /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
+ *
+ * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
+ * Target View Extent, and Depth Coordinate Offset X/Y of the
+ * hierarchical depth buffer are inherited from the depth buffer. The
+ * height and width of the hierarchical depth buffer that must be
+ * allocated are computed by the following formulas, where HZ is the
+ * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
+ * Z_Width, and Z_Depth values given in these formulas are those present
+ * in 3DSTATE_DEPTH_BUFFER incremented by one.
+ *
+ * "The value of Z_Height and Z_Width must each be multiplied by 2 before
+ * being applied to the table below if Number of Multisamples is set to
+ * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
+ * Z_Width must be multiplied by 4 before being applied to the table
+ * below if Number of Multisamples is set to NUMSAMPLES_8."
+ *
+ * In the Sky Lake PRM, the second paragraph is replaced with this:
+ *
+ * "The Z_Height and Z_Width values must equal those present in
+ * 3DSTATE_DEPTH_BUFFER incremented by one."
+ *
+ * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
+ * block corresponds to a region of 8x4 samples in the primary depth
+ * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
+ * a region of 8x4 pixels in the primary depth surface regardless of the
+ * number of samples. The dimensions of a HiZ block in both pixels and
+ * samples are given in the table below:
+ *
+ * | SNB - BDW | SKL+
+ * ------+-----------+-------------
+ * 1x | 8 x 4 sa | 8 x 4 sa
+ * MSAA | 8 x 4 px | 8 x 4 px
+ * ------+-----------+-------------
+ * 2x | 8 x 4 sa | 16 x 4 sa
+ * MSAA | 4 x 4 px | 8 x 4 px
+ * ------+-----------+-------------
+ * 4x | 8 x 4 sa | 16 x 8 sa
+ * MSAA | 4 x 2 px | 8 x 4 px
+ * ------+-----------+-------------
+ * 8x | 8 x 4 sa | 32 x 8 sa
+ * MSAA | 2 x 2 px | 8 x 4 px
+ * ------+-----------+-------------
+ * 16x | N/A | 32 x 16 sa
+ * MSAA | N/A | 8 x 4 px
+ * ------+-----------+-------------
+ *
+ * There are a number of different ways that this discrepency could be
+ * handled. The way we have chosen is to simply make MSAA HiZ have the
+ * same number of samples as the parent surface pre-Sky Lake and always be
+ * single-sampled on Sky Lake and above. Since the block sizes of
+ * compressed formats are given in samples, this neatly handles everything
+ * without the need for additional HiZ formats with different block sizes
+ * on SKL+.
+ */
+ const unsigned samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples;
+
+ return isl_surf_init(dev, hiz_surf,
+ .dim = surf->dim,
+ .format = ISL_FORMAT_HIZ,
+ .width = surf->logical_level0_px.width,
+ .height = surf->logical_level0_px.height,
+ .depth = surf->logical_level0_px.depth,
+ .levels = surf->levels,
+ .array_len = surf->logical_level0_px.array_len,
+ .samples = samples,
+ .usage = ISL_SURF_USAGE_HIZ_BIT,
+ .tiling_flags = ISL_TILING_HIZ_BIT);
}
-void
+bool
isl_surf_get_mcs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *mcs_surf)
assert(surf->levels == 1);
assert(surf->logical_level0_px.depth == 1);
+ /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
+ * bits which means the maximum pitch of a compression surface is 512
+ * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
+ * 64bpp, this gives us a maximum width of 8192 pixels. We can create
+ * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
+ * and 8x, we have enough room for the full 16k supported by the hardware.
+ */
+ if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
+ return false;
+
enum isl_format mcs_format;
switch (surf->samples) {
case 2: mcs_format = ISL_FORMAT_MCS_2X; break;
unreachable("Invalid sample count");
}
- isl_surf_init(dev, mcs_surf,
- .dim = ISL_SURF_DIM_2D,
- .format = mcs_format,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = 1,
- .levels = 1,
- .array_len = surf->logical_level0_px.array_len,
- .samples = 1, /* MCS surfaces are really single-sampled */
- .usage = ISL_SURF_USAGE_MCS_BIT,
- .tiling_flags = ISL_TILING_Y0_BIT);
+ return isl_surf_init(dev, mcs_surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = mcs_format,
+ .width = surf->logical_level0_px.width,
+ .height = surf->logical_level0_px.height,
+ .depth = 1,
+ .levels = 1,
+ .array_len = surf->logical_level0_px.array_len,
+ .samples = 1, /* MCS surfaces are really single-sampled */
+ .usage = ISL_SURF_USAGE_MCS_BIT,
+ .tiling_flags = ISL_TILING_Y0_BIT);
}
bool
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
- struct isl_surf *ccs_surf)
+ struct isl_surf *ccs_surf,
+ uint32_t row_pitch)
{
assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(ISL_DEV_GEN(dev) >= 7);
- assert(surf->dim == ISL_SURF_DIM_2D);
- assert(surf->logical_level0_px.depth == 1);
+ if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
+ return false;
+
+ /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+ * work for 3D textures until gen9 where the layout of 3D textures changes
+ * to match 2D array textures.
+ */
+ if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
+ return false;
+
+ /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
+ * Non-MultiSampler Render Target Restrictions):
+ *
+ * "Support is for non-mip-mapped and non-array surface types only."
+ *
+ * This restriction is lifted on gen8+. Technically, it may be possible to
+ * create a CCS for an arrayed or mipmapped image and only enable CCS_D
+ * when rendering to the base slice. However, there is no documentation
+ * tell us what the hardware would do in that case or what it does if you
+ * walk off the bases slice. (Does it ignore CCS or does it start
+ * scribbling over random memory?) We play it safe and just follow the
+ * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
+ */
+ if (ISL_DEV_GEN(dev) <= 7 &&
+ (surf->levels > 1 || surf->logical_level0_px.array_len > 1))
+ return false;
+
+ if (isl_format_is_compressed(surf->format))
+ return false;
/* TODO: More conditions where it can fail. */
return false;
}
- isl_surf_init(dev, ccs_surf,
- .dim = ISL_SURF_DIM_2D,
- .format = ccs_format,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = 1,
- .levels = surf->levels,
- .array_len = surf->logical_level0_px.array_len,
- .samples = 1,
- .usage = ISL_SURF_USAGE_CCS_BIT,
- .tiling_flags = ISL_TILING_CCS_BIT);
-
- return true;
+ return isl_surf_init(dev, ccs_surf,
+ .dim = surf->dim,
+ .format = ccs_format,
+ .width = surf->logical_level0_px.width,
+ .height = surf->logical_level0_px.height,
+ .depth = surf->logical_level0_px.depth,
+ .levels = surf->levels,
+ .array_len = surf->logical_level0_px.array_len,
+ .samples = 1,
+ .row_pitch = row_pitch,
+ .usage = ISL_SURF_USAGE_CCS_BIT,
+ .tiling_flags = ISL_TILING_CCS_BIT);
}
+#define isl_genX_call(dev, func, ...) \
+ switch (ISL_DEV_GEN(dev)) { \
+ case 4: \
+ /* G45 surface state is the same as gen5 */ \
+ if (ISL_DEV_IS_G4X(dev)) { \
+ isl_gen5_##func(__VA_ARGS__); \
+ } else { \
+ isl_gen4_##func(__VA_ARGS__); \
+ } \
+ break; \
+ case 5: \
+ isl_gen5_##func(__VA_ARGS__); \
+ break; \
+ case 6: \
+ isl_gen6_##func(__VA_ARGS__); \
+ break; \
+ case 7: \
+ if (ISL_DEV_IS_HASWELL(dev)) { \
+ isl_gen75_##func(__VA_ARGS__); \
+ } else { \
+ isl_gen7_##func(__VA_ARGS__); \
+ } \
+ break; \
+ case 8: \
+ isl_gen8_##func(__VA_ARGS__); \
+ break; \
+ case 9: \
+ isl_gen9_##func(__VA_ARGS__); \
+ break; \
+ case 10: \
+ isl_gen10_##func(__VA_ARGS__); \
+ break; \
+ case 11: \
+ isl_gen11_##func(__VA_ARGS__); \
+ break; \
+ default: \
+ assert(!"Unknown hardware generation"); \
+ }
+
void
isl_surf_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_surf_fill_state_info *restrict info)
info->surf->logical_level0_px.array_len);
}
- switch (ISL_DEV_GEN(dev)) {
- case 4:
- if (ISL_DEV_IS_G4X(dev)) {
- /* G45 surface state is the same as gen5 */
- isl_gen5_surf_fill_state_s(dev, state, info);
- } else {
- isl_gen4_surf_fill_state_s(dev, state, info);
- }
- break;
- case 5:
- isl_gen5_surf_fill_state_s(dev, state, info);
- break;
- case 6:
- isl_gen6_surf_fill_state_s(dev, state, info);
- break;
- case 7:
- if (ISL_DEV_IS_HASWELL(dev)) {
- isl_gen75_surf_fill_state_s(dev, state, info);
- } else {
- isl_gen7_surf_fill_state_s(dev, state, info);
- }
- break;
- case 8:
- isl_gen8_surf_fill_state_s(dev, state, info);
- break;
- case 9:
- isl_gen9_surf_fill_state_s(dev, state, info);
- break;
- default:
- assert(!"Cannot fill surface state for this gen");
- }
+ isl_genX_call(dev, surf_fill_state_s, dev, state, info);
}
void
isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
- switch (ISL_DEV_GEN(dev)) {
- case 4:
- case 5:
- /* Gen 4-5 are all the same when it comes to buffer surfaces */
- isl_gen5_buffer_fill_state_s(state, info);
- break;
- case 6:
- isl_gen6_buffer_fill_state_s(state, info);
- break;
- case 7:
- if (ISL_DEV_IS_HASWELL(dev)) {
- isl_gen75_buffer_fill_state_s(state, info);
+ isl_genX_call(dev, buffer_fill_state_s, state, info);
+}
+
+void
+isl_null_fill_state(const struct isl_device *dev, void *state,
+ struct isl_extent3d size)
+{
+ isl_genX_call(dev, null_fill_state, state, size);
+}
+
+void
+isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+ const struct isl_depth_stencil_hiz_emit_info *restrict info)
+{
+ if (info->depth_surf && info->stencil_surf) {
+ if (!dev->info->has_hiz_and_separate_stencil) {
+ assert(info->depth_surf == info->stencil_surf);
+ assert(info->depth_address == info->stencil_address);
+ }
+ assert(info->depth_surf->dim == info->stencil_surf->dim);
+ }
+
+ if (info->depth_surf) {
+ assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
+ if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.depth);
} else {
- isl_gen7_buffer_fill_state_s(state, info);
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.array_len);
}
- break;
- case 8:
- isl_gen8_buffer_fill_state_s(state, info);
- break;
- case 9:
- isl_gen9_buffer_fill_state_s(state, info);
- break;
- default:
- assert(!"Cannot fill surface state for this gen");
}
+
+ if (info->stencil_surf) {
+ assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
+ if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.depth);
+ } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.array_len);
+ }
+ }
+
+ isl_genX_call(dev, emit_depth_stencil_hiz_s, dev, batch, info);
}
/**
uint32_t *y_offset_sa)
{
assert(level < surf->levels);
- assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
- assert(surf->phys_level0_sa.array_len == 1);
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ assert(surf->phys_level0_sa.array_len == 1);
+ assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
+ } else {
+ assert(surf->dim == ISL_SURF_DIM_2D);
+ assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
+ assert(surf->phys_level0_sa.array_len == 6);
+ assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
+ }
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
const uint32_t W0 = surf->phys_level0_sa.width;
const uint32_t H0 = surf->phys_level0_sa.height;
const uint32_t D0 = surf->phys_level0_sa.depth;
+ const uint32_t AL = surf->phys_level0_sa.array_len;
uint32_t x = 0;
uint32_t y = 0;
for (uint32_t l = 0; l < level; ++l) {
const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
+ image_align_sa.d);
const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
y += level_h * max_layers_vert;
const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
+ image_align_sa.d);
const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
*y_offset_sa = y;
}
+static void
+get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+ assert(level < surf->levels);
+ assert(surf->logical_level0_px.depth == 1);
+ assert(logical_array_layer < surf->logical_level0_px.array_len);
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ const struct isl_extent3d image_align_sa =
+ isl_surf_get_image_alignment_sa(surf);
+
+ struct isl_tile_info tile_info;
+ isl_tiling_get_info(surf->tiling, fmtl->bpb, &tile_info);
+ const struct isl_extent2d tile_extent_sa = {
+ .w = tile_info.logical_extent_el.w * fmtl->bw,
+ .h = tile_info.logical_extent_el.h * fmtl->bh,
+ };
+ /* Tile size is a multiple of image alignment */
+ assert(tile_extent_sa.w % image_align_sa.w == 0);
+ assert(tile_extent_sa.h % image_align_sa.h == 0);
+
+ const uint32_t W0 = surf->phys_level0_sa.w;
+ const uint32_t H0 = surf->phys_level0_sa.h;
+
+ /* Each image has the same height as LOD0 because the hardware thinks
+ * everything is LOD0
+ */
+ const uint32_t H = isl_align(H0, image_align_sa.h);
+
+ /* Quick sanity check for consistency */
+ if (surf->phys_level0_sa.array_len > 1)
+ assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
+
+ uint32_t x = 0, y = 0;
+ for (uint32_t l = 0; l < level; ++l) {
+ const uint32_t W = isl_minify(W0, l);
+
+ const uint32_t w = isl_align(W, tile_extent_sa.w);
+ const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
+ tile_extent_sa.h);
+
+ if (l == 0) {
+ y += h;
+ } else {
+ x += w;
+ }
+ }
+
+ y += H * logical_array_layer;
+
+ *x_offset_sa = x;
+ *y_offset_sa = y;
+}
+
/**
* A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN9_1D.
x_offset_sa, y_offset_sa);
break;
case ISL_DIM_LAYOUT_GEN4_3D:
- get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px,
+ get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
+ logical_z_offset_px,
x_offset_sa, y_offset_sa);
break;
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer +
+ logical_z_offset_px,
+ x_offset_sa, y_offset_sa);
+ break;
default:
unreachable("not reached");
}
void
-isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
- enum isl_tiling tiling,
- uint8_t bs,
+isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ uint32_t *offset_B,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ uint32_t total_x_offset_el, total_y_offset_el;
+ isl_surf_get_image_offset_el(surf, level, logical_array_layer,
+ logical_z_offset_px,
+ &total_x_offset_el,
+ &total_y_offset_el);
+
+ uint32_t x_offset_el, y_offset_el;
+ isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
+ surf->row_pitch,
+ total_x_offset_el,
+ total_y_offset_el,
+ offset_B,
+ &x_offset_el,
+ &y_offset_el);
+
+ if (x_offset_sa) {
+ *x_offset_sa = x_offset_el * fmtl->bw;
+ } else {
+ assert(x_offset_el == 0);
+ }
+
+ if (y_offset_sa) {
+ *y_offset_sa = y_offset_el * fmtl->bh;
+ } else {
+ assert(y_offset_el == 0);
+ }
+}
+
+void
+isl_surf_get_image_surf(const struct isl_device *dev,
+ const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ struct isl_surf *image_surf,
+ uint32_t *offset_B,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+ isl_surf_get_image_offset_B_tile_sa(surf,
+ level,
+ logical_array_layer,
+ logical_z_offset_px,
+ offset_B,
+ x_offset_sa,
+ y_offset_sa);
+
+ /* Even for cube maps there will be only single face, therefore drop the
+ * corresponding flag if present.
+ */
+ const isl_surf_usage_flags_t usage =
+ surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
+
+ bool ok UNUSED;
+ ok = isl_surf_init(dev, image_surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = surf->format,
+ .width = isl_minify(surf->logical_level0_px.w, level),
+ .height = isl_minify(surf->logical_level0_px.h, level),
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = surf->samples,
+ .row_pitch = surf->row_pitch,
+ .usage = usage,
+ .tiling_flags = (1 << surf->tiling));
+ assert(ok);
+}
+
+void
+isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
+ uint32_t bpb,
uint32_t row_pitch,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *x_offset_el,
uint32_t *y_offset_el)
{
- /* This function only really works for power-of-two surfaces. In
- * theory, we could make it work for non-power-of-two surfaces by going
- * to the left until we find a block that is bs-aligned. The Vulkan
- * driver doesn't use non-power-of-two tiled surfaces so we'll leave
- * this unimplemented for now.
- */
- assert(tiling == ISL_TILING_LINEAR || isl_is_pow2(bs));
-
if (tiling == ISL_TILING_LINEAR) {
+ assert(bpb % 8 == 0);
*base_address_offset = total_y_offset_el * row_pitch +
- total_x_offset_el * bs;
+ total_x_offset_el * (bpb / 8);
*x_offset_el = 0;
*y_offset_el = 0;
return;
}
struct isl_tile_info tile_info;
- isl_tiling_get_info(dev, tiling, bs * 8, &tile_info);
+ isl_tiling_get_info(tiling, bpb, &tile_info);
+
+ assert(row_pitch % tile_info.phys_extent_B.width == 0);
+
+ /* For non-power-of-two formats, we need the address to be both tile and
+ * element-aligned. The easiest way to achieve this is to work with a tile
+ * that is three times as wide as the regular tile.
+ *
+ * The tile info returned by get_tile_info has a logical size that is an
+ * integer number of tile_info.format_bpb size elements. To scale the
+ * tile, we scale up the physical width and then treat the logical tile
+ * size as if it has bpb size elements.
+ */
+ const uint32_t tile_el_scale = bpb / tile_info.format_bpb;
+ tile_info.phys_extent_B.width *= tile_el_scale;
/* Compute the offset into the tile */
*x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w;
uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w;
uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
- assert(row_pitch % tile_info.phys_extent_B.width == 0);
*base_address_offset =
y_offset_tl * tile_info.phys_extent_B.h * row_pitch +
x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
projects / mesa.git / blobdiff