};
}
+bool
+isl_color_value_is_zero(union isl_color_value value,
+ enum isl_format format)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+#define RETURN_FALSE_IF_NOT_0(c, i) \
+ if (fmtl->channels.c.bits && value.u32[i] != 0) \
+ return false
+
+ RETURN_FALSE_IF_NOT_0(r, 0);
+ RETURN_FALSE_IF_NOT_0(g, 1);
+ RETURN_FALSE_IF_NOT_0(b, 2);
+ RETURN_FALSE_IF_NOT_0(a, 3);
+
+#undef RETURN_FALSE_IF_NOT_0
+
+ return true;
+}
+
bool
isl_color_value_is_zero_one(union isl_color_value value,
enum isl_format format)
!pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
return false;
- if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
- isl_finishme("validate row pitch of stencil surfaces");
+ const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
+ _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
+ _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
+
+ if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
+ !pitch_in_range(row_pitch, stencil_pitch_bits))
+ return false;
done:
*out_row_pitch = row_pitch;
*/
if (size > (uint64_t) 1 << 31)
return false;
- } else {
+ } else if (ISL_DEV_GEN(dev) < 11) {
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
* "In addition to restrictions on maximum height, width, and depth,
* surfaces are also restricted to a maximum size of 2^38 bytes.
*/
if (size > (uint64_t) 1 << 38)
return false;
+ } else {
+ /* gen11+ platforms raised this limit to 2^44 bytes. */
+ if (size > (uint64_t) 1 << 44)
+ return false;
}
*surf = (struct isl_surf) {
.tiling_flags = ISL_TILING_CCS_BIT);
}
+#define isl_genX_call(dev, func, ...) \
+ switch (ISL_DEV_GEN(dev)) { \
+ case 4: \
+ /* G45 surface state is the same as gen5 */ \
+ if (ISL_DEV_IS_G4X(dev)) { \
+ isl_gen5_##func(__VA_ARGS__); \
+ } else { \
+ isl_gen4_##func(__VA_ARGS__); \
+ } \
+ break; \
+ case 5: \
+ isl_gen5_##func(__VA_ARGS__); \
+ break; \
+ case 6: \
+ isl_gen6_##func(__VA_ARGS__); \
+ break; \
+ case 7: \
+ if (ISL_DEV_IS_HASWELL(dev)) { \
+ isl_gen75_##func(__VA_ARGS__); \
+ } else { \
+ isl_gen7_##func(__VA_ARGS__); \
+ } \
+ break; \
+ case 8: \
+ isl_gen8_##func(__VA_ARGS__); \
+ break; \
+ case 9: \
+ isl_gen9_##func(__VA_ARGS__); \
+ break; \
+ case 10: \
+ isl_gen10_##func(__VA_ARGS__); \
+ break; \
+ case 11: \
+ isl_gen11_##func(__VA_ARGS__); \
+ break; \
+ default: \
+ assert(!"Unknown hardware generation"); \
+ }
+
void
isl_surf_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_surf_fill_state_info *restrict info)
info->surf->logical_level0_px.array_len);
}
- switch (ISL_DEV_GEN(dev)) {
- case 4:
- if (ISL_DEV_IS_G4X(dev)) {
- /* G45 surface state is the same as gen5 */
- isl_gen5_surf_fill_state_s(dev, state, info);
- } else {
- isl_gen4_surf_fill_state_s(dev, state, info);
- }
- break;
- case 5:
- isl_gen5_surf_fill_state_s(dev, state, info);
- break;
- case 6:
- isl_gen6_surf_fill_state_s(dev, state, info);
- break;
- case 7:
- if (ISL_DEV_IS_HASWELL(dev)) {
- isl_gen75_surf_fill_state_s(dev, state, info);
- } else {
- isl_gen7_surf_fill_state_s(dev, state, info);
- }
- break;
- case 8:
- isl_gen8_surf_fill_state_s(dev, state, info);
- break;
- case 9:
- isl_gen9_surf_fill_state_s(dev, state, info);
- break;
- case 10:
- isl_gen10_surf_fill_state_s(dev, state, info);
- break;
- default:
- assert(!"Cannot fill surface state for this gen");
- }
+ isl_genX_call(dev, surf_fill_state_s, dev, state, info);
}
void
isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
- switch (ISL_DEV_GEN(dev)) {
- case 4:
- case 5:
- /* Gen 4-5 are all the same when it comes to buffer surfaces */
- isl_gen5_buffer_fill_state_s(state, info);
- break;
- case 6:
- isl_gen6_buffer_fill_state_s(state, info);
- break;
- case 7:
- if (ISL_DEV_IS_HASWELL(dev)) {
- isl_gen75_buffer_fill_state_s(state, info);
- } else {
- isl_gen7_buffer_fill_state_s(state, info);
- }
- break;
- case 8:
- isl_gen8_buffer_fill_state_s(state, info);
- break;
- case 9:
- isl_gen9_buffer_fill_state_s(state, info);
- break;
- case 10:
- isl_gen10_buffer_fill_state_s(state, info);
- break;
- default:
- assert(!"Cannot fill surface state for this gen");
- }
+ isl_genX_call(dev, buffer_fill_state_s, state, info);
+}
+
+void
+isl_null_fill_state(const struct isl_device *dev, void *state,
+ struct isl_extent3d size)
+{
+ isl_genX_call(dev, null_fill_state, state, size);
}
void
}
}
- switch (ISL_DEV_GEN(dev)) {
- case 4:
- if (ISL_DEV_IS_G4X(dev)) {
- /* G45 surface state is the same as gen5 */
- isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
- } else {
- isl_gen4_emit_depth_stencil_hiz_s(dev, batch, info);
- }
- break;
- case 5:
- isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
- break;
- case 6:
- isl_gen6_emit_depth_stencil_hiz_s(dev, batch, info);
- break;
- case 7:
- if (ISL_DEV_IS_HASWELL(dev)) {
- isl_gen75_emit_depth_stencil_hiz_s(dev, batch, info);
- } else {
- isl_gen7_emit_depth_stencil_hiz_s(dev, batch, info);
- }
- break;
- case 8:
- isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
- break;
- case 9:
- isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
- break;
- case 10:
- isl_gen10_emit_depth_stencil_hiz_s(dev, batch, info);
- break;
- default:
- assert(!"Cannot fill surface state for this gen");
- }
+ isl_genX_call(dev, emit_depth_stencil_hiz_s, dev, batch, info);
}
/**
projects / mesa.git / blobdiff