intel/isl/gen6: Allow arrayed stencil

[mesa.git] / src / intel / isl / isl.c

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 60a594394b91486374438013aa5b96def9e09c86..2449ffb29ae01c662f51d585e7804a40c27a0cbc 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -447,7 +447,6 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
           *    the storage for LODs other than LOD 0 is not needed.
           */
          assert(info->levels == 1);
-         assert(phys_level0_sa->array_len == 1);
          return ISL_ARRAY_PITCH_SPAN_COMPACT;
       } else {
          if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) &&
@@ -1467,7 +1466,8 @@ isl_surf_init_s(const struct isl_device *dev,
                            &phys_total_el, &row_pitch))
       return false;
 
-   uint32_t size, base_alignment;
+   uint32_t base_alignment;
+   uint64_t size;
    if (tiling == ISL_TILING_LINEAR) {
       size = row_pitch * padded_h_el + pad_bytes;
 
@@ -1502,6 +1502,28 @@ isl_surf_init_s(const struct isl_device *dev,
       base_alignment = MAX(info->min_alignment, tile_size);
    }
 
+   if (ISL_DEV_GEN(dev) < 9) {
+      /* From the Broadwell PRM Vol 5, Surface Layout:
+       *
+       *    "In addition to restrictions on maximum height, width, and depth,
+       *     surfaces are also restricted to a maximum size in bytes. This
+       *     maximum is 2 GB for all products and all surface types."
+       *
+       * This comment is applicable to all Pre-gen9 platforms.
+       */
+      if (size > (uint64_t) 1 << 31)
+         return false;
+   } else {
+      /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
+       *    "In addition to restrictions on maximum height, width, and depth,
+       *     surfaces are also restricted to a maximum size of 2^38 bytes.
+       *     All pixels within the surface must be contained within 2^38 bytes
+       *     of the base address."
+       */
+      if (size > (uint64_t) 1 << 38)
+         return false;
+   }
+
    *surf = (struct isl_surf) {
       .dim = info->dim,
       .dim_layout = dim_layout,
@@ -1778,6 +1800,9 @@ isl_surf_fill_state_s(const struct isl_device *dev, void *state,
    case 9:
       isl_gen9_surf_fill_state_s(dev, state, info);
       break;
+   case 10:
+      isl_gen10_surf_fill_state_s(dev, state, info);
+      break;
    default:
       assert(!"Cannot fill surface state for this gen");
    }
@@ -1809,6 +1834,9 @@ isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
    case 9:
       isl_gen9_buffer_fill_state_s(state, info);
       break;
+   case 10:
+      isl_gen10_buffer_fill_state_s(state, info);
+      break;
    default:
       assert(!"Cannot fill surface state for this gen");
    }
@@ -1876,6 +1904,9 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
    case 9:
       isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
       break;
+   case 10:
+      isl_gen10_emit_depth_stencil_hiz_s(dev, batch, info);
+      break;
    default:
       assert(!"Cannot fill surface state for this gen");
    }