#include <stdarg.h>
#include <stdio.h>
+#include "genxml/genX_bits.h"
+
#include "isl.h"
#include "isl_gen4.h"
#include "isl_gen6.h"
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
}
-static const struct {
- uint8_t size;
- uint8_t align;
- uint8_t addr_offset;
- uint8_t aux_addr_offset;
-} ss_infos[] = {
- [4] = {24, 32, 4},
- [5] = {24, 32, 4},
- [6] = {24, 32, 4},
- [7] = {32, 32, 4, 24},
- [8] = {64, 64, 32, 40},
- [9] = {64, 64, 32, 40},
-};
-
void
isl_device_init(struct isl_device *dev,
const struct gen_device_info *info,
if (info->must_use_separate_stencil)
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
- dev->ss.size = ss_infos[ISL_DEV_GEN(dev)].size;
- dev->ss.align = ss_infos[ISL_DEV_GEN(dev)].align;
- dev->ss.addr_offset = ss_infos[ISL_DEV_GEN(dev)].addr_offset;
- dev->ss.aux_addr_offset = ss_infos[ISL_DEV_GEN(dev)].aux_addr_offset;
+ dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
+ dev->ss.align = isl_align(dev->ss.size, 32);
+
+ assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ss.addr_offset =
+ RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
+
+ /* The "Auxiliary Surface Base Address" field starts a bit higher up
+ * because the bottom 12 bits are used for other things. Round down to
+ * the nearest dword before.
+ */
+ dev->ss.aux_addr_offset =
+ (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
+
+ dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
+ assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.depth_offset =
+ _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ if (dev->use_separate_stencil) {
+ dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_CLEAR_PARAMS_length(info) * 4;
+
+ assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.stencil_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.hiz_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+ } else {
+ dev->ds.stencil_offset = 0;
+ dev->ds.hiz_offset = 0;
+ }
}
/**
/**
* @param[out] info is written only on success
*/
-static bool
-isl_tiling_get_info(const struct isl_device *dev,
- enum isl_tiling tiling,
+static void
+isl_tiling_get_info(enum isl_tiling tiling,
uint32_t format_bpb,
struct isl_tile_info *tile_info)
{
*/
assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
- return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info);
+ isl_tiling_get_info(tiling, format_bpb / 3, tile_info);
+ return;
}
switch (tiling) {
case ISL_TILING_Yf:
case ISL_TILING_Ys: {
- if (ISL_DEV_GEN(dev) < 9)
- return false;
-
- if (!isl_is_pow2(bs))
- return false;
-
bool is_Ys = tiling == ISL_TILING_Ys;
assert(bs > 0);
.logical_extent_el = logical_el,
.phys_extent_B = phys_B,
};
-
- return true;
}
/**
if (ISL_DEV_GEN(dev) >= 6) {
isl_gen6_filter_tiling(dev, info, &tiling_flags);
} else {
- isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
- isl_gen6_filter_tiling(dev, info, &tiling_flags);
+ isl_gen4_filter_tiling(dev, info, &tiling_flags);
}
#define CHOOSE(__tiling) \
* the storage for LODs other than LOD 0 is not needed.
*/
assert(info->levels == 1);
- assert(phys_level0_sa->array_len == 1);
return ISL_ARRAY_PITCH_SPAN_COMPACT;
} else {
if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) &&
* compact QPitch possible in order to conserve memory.
*/
return ISL_ARRAY_PITCH_SPAN_COMPACT;
+
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ /* Each array image in the gen6 stencil of HiZ surface is compact in the
+ * sense that every LOD is a compact array of the same size as LOD0.
+ */
+ return ISL_ARRAY_PITCH_SPAN_COMPACT;
}
unreachable("bad isl_dim_layout");
return;
} else if (info->format == ISL_FORMAT_HIZ) {
assert(ISL_DEV_GEN(dev) >= 6);
- /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
- * which works out to 2x2 HiZ elments.
- */
- *image_align_el = isl_extent3d(2, 2, 1);
+ if (ISL_DEV_GEN(dev) == 6) {
+ /* HiZ surfaces on Sandy Bridge are packed tightly. */
+ *image_align_el = isl_extent3d(1, 1, 1);
+ } else {
+ /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
+ * primary surface which works out to 2x2 HiZ elments.
+ */
+ *image_align_el = isl_extent3d(2, 2, 1);
+ }
return;
}
enum isl_surf_dim logical_dim,
enum isl_tiling tiling)
{
+ /* Sandy bridge needs a special layout for HiZ and stencil. */
+ if (ISL_DEV_GEN(dev) == 6 &&
+ (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
+ return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ;
+
if (ISL_DEV_GEN(dev) >= 9) {
switch (logical_dim) {
case ISL_SURF_DIM_1D:
case ISL_DIM_LAYOUT_GEN9_1D:
case ISL_DIM_LAYOUT_GEN4_2D:
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
*phys_level0_sa = (struct isl_extent4d) {
.w = isl_align_npot(info->width, fmtl->bw),
.h = fmtl->bh,
break;
case ISL_SURF_DIM_2D:
- assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D);
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
+ dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
if (tiling == ISL_TILING_Ys && info->samples > 1)
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN4_2D:
}
}
+/**
+ * Calculate the pitch between physical array slices, in units of rows of
+ * surface elements.
+ */
+static uint32_t
+isl_calc_array_pitch_el_rows_gen4_2d(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ const struct isl_extent2d *phys_slice0_sa)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ uint32_t pitch_sa_rows = 0;
+
+ switch (array_pitch_span) {
+ case ISL_ARRAY_PITCH_SPAN_COMPACT:
+ pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
+ break;
+ case ISL_ARRAY_PITCH_SPAN_FULL: {
+ /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
+ * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
+ * Surfaces >> Surface Arrays.
+ */
+ uint32_t H0_sa = phys_level0_sa->h;
+ uint32_t H1_sa = isl_minify(H0_sa, 1);
+
+ uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
+ uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
+
+ uint32_t m;
+ if (ISL_DEV_GEN(dev) >= 7) {
+ /* The QPitch equation changed slightly in Ivybridge. */
+ m = 12;
+ } else {
+ m = 11;
+ }
+
+ pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
+
+ if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
+ (info->height % 4 == 1)) {
+ /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
+ * Graphics Core >> Section 7.18.3.7: Surface Arrays:
+ *
+ * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
+ * the value calculated in the equation above , for every
+ * other odd Surface Height starting from 1 i.e. 1,5,9,13.
+ *
+ * XXX(chadv): Is the errata natural corollary of the physical
+ * layout of interleaved samples?
+ */
+ pitch_sa_rows += 4;
+ }
+
+ pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
+ } /* end case */
+ break;
+ }
+
+ assert(pitch_sa_rows % fmtl->bh == 0);
+ uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
+
+ if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
+ /*
+ * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
+ *
+ * "Mip-mapped and arrayed surfaces are supported with MCS buffer
+ * layout with these alignments in the RT space: Horizontal
+ * Alignment = 128 and Vertical Alignment = 64."
+ *
+ * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
+ *
+ * "For non-multisampled render target's CCS auxiliary surface,
+ * QPitch must be computed with Horizontal Alignment = 128 and
+ * Surface Vertical Alignment = 256. These alignments are only for
+ * CCS buffer and not for associated render target."
+ *
+ * The first restriction is already handled by isl_choose_image_alignment_el
+ * but the second restriction, which is an extension of the first, only
+ * applies to qpitch and must be applied here.
+ */
+ assert(fmtl->bh == 4);
+ pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
+ }
+
+ if (ISL_DEV_GEN(dev) >= 9 &&
+ info->dim == ISL_SURF_DIM_3D &&
+ tile_info->tiling != ISL_TILING_LINEAR) {
+ /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
+ *
+ * Tile Mode != Linear: This field must be set to an integer multiple
+ * of the tile height
+ */
+ pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
+ }
+
+ return pitch_el_rows;
+}
+
/**
* A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_2D.
};
}
+static void
+isl_calc_phys_total_extent_el_gen4_2d(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ enum isl_msaa_layout msaa_layout,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *total_extent_el)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
+ struct isl_extent2d phys_slice0_sa;
+ isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout,
+ image_align_sa, phys_level0_sa,
+ &phys_slice0_sa);
+ *array_pitch_el_rows =
+ isl_calc_array_pitch_el_rows_gen4_2d(dev, info, tile_info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_span,
+ &phys_slice0_sa);
+ *total_extent_el = (struct isl_extent2d) {
+ .w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
+ .h = *array_pitch_el_rows * phys_level0_sa->array_len,
+ };
+}
+
/**
* A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_3D.
*/
static void
-isl_calc_phys_slice0_extent_sa_gen4_3d(
+isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
assert(info->samples == 1);
assert(phys_level0_sa->array_len == 1);
- uint32_t slice_w = 0;
- uint32_t slice_h = 0;
+ uint32_t total_w = 0;
+ uint32_t total_h = 0;
uint32_t W0 = phys_level0_sa->w;
uint32_t H0 = phys_level0_sa->h;
uint32_t max_layers_horiz = MIN(level_d, 1u << l);
uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
- slice_w = MAX(slice_w, level_w * max_layers_horiz);
- slice_h += level_h * max_layers_vert;
+ total_w = MAX(total_w, level_w * max_layers_horiz);
+ total_h += level_h * max_layers_vert;
}
- *phys_slice0_sa = (struct isl_extent2d) {
- .w = slice_w,
- .h = slice_h,
+ /* GEN4_3D layouts don't really have an array pitch since each LOD has a
+ * different number of horizontal and vertical layers. We have to set it
+ * to something, so at least make it true for LOD0.
+ */
+ *array_pitch_el_rows =
+ isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(total_w, fmtl->bw),
+ .h = isl_assert_div(total_h, fmtl->bh),
+ };
+}
+
+/**
+ * A variant of isl_calc_phys_slice0_extent_sa() specific to
+ * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
+ */
+static void
+isl_calc_phys_total_extent_el_gen6_stencil_hiz(
+ const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
+ const struct isl_extent2d tile_extent_sa = {
+ .w = tile_info->logical_extent_el.w * fmtl->bw,
+ .h = tile_info->logical_extent_el.h * fmtl->bh,
+ };
+ /* Tile size is a multiple of image alignment */
+ assert(tile_extent_sa.w % image_align_sa->w == 0);
+ assert(tile_extent_sa.h % image_align_sa->h == 0);
+
+ const uint32_t W0 = phys_level0_sa->w;
+ const uint32_t H0 = phys_level0_sa->h;
+
+ /* Each image has the same height as LOD0 because the hardware thinks
+ * everything is LOD0
+ */
+ const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a;
+
+ uint32_t total_top_w = 0;
+ uint32_t total_bottom_w = 0;
+ uint32_t total_h = 0;
+
+ for (uint32_t l = 0; l < info->levels; ++l) {
+ const uint32_t W = isl_minify(W0, l);
+
+ const uint32_t w = isl_align(W, tile_extent_sa.w);
+ const uint32_t h = isl_align(H, tile_extent_sa.h);
+
+ if (l == 0) {
+ total_top_w = w;
+ total_h = h;
+ } else if (l == 1) {
+ total_bottom_w = w;
+ total_h += h;
+ } else {
+ total_bottom_w += w;
+ }
+ }
+
+ *array_pitch_el_rows =
+ isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
+ .h = isl_assert_div(total_h, fmtl->bh),
};
}
* ISL_DIM_LAYOUT_GEN9_1D.
*/
static void
-isl_calc_phys_slice0_extent_sa_gen9_1d(
+isl_calc_phys_total_extent_el_gen9_1d(
const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *phys_total_el)
{
MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
slice_w += w;
}
- *phys_slice0_sa = isl_extent2d(slice_w, 1);
+ *array_pitch_el_rows = 1;
+ *phys_total_el = (struct isl_extent2d) {
+ .w = isl_assert_div(slice_w, fmtl->bw),
+ .h = phys_level0_sa->array_len,
+ };
}
/**
- * Calculate the physical extent of the surface's first array slice, in units
- * of surface samples. If the surface is multi-leveled, then the result will
- * be aligned to \a image_align_sa.
+ * Calculate the two-dimensional total physical extent of the surface, in
+ * units of surface elements.
*/
static void
-isl_calc_phys_slice0_extent_sa(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- enum isl_dim_layout dim_layout,
- enum isl_msaa_layout msaa_layout,
- const struct isl_extent3d *image_align_sa,
- const struct isl_extent4d *phys_level0_sa,
- struct isl_extent2d *phys_slice0_sa)
+isl_calc_phys_total_extent_el(const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
+ enum isl_dim_layout dim_layout,
+ enum isl_msaa_layout msaa_layout,
+ const struct isl_extent3d *image_align_sa,
+ const struct isl_extent4d *phys_level0_sa,
+ enum isl_array_pitch_span array_pitch_span,
+ uint32_t *array_pitch_el_rows,
+ struct isl_extent2d *total_extent_el)
{
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
- isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info,
- image_align_sa, phys_level0_sa,
- phys_slice0_sa);
+ assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+ isl_calc_phys_total_extent_el_gen9_1d(dev, info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
return;
case ISL_DIM_LAYOUT_GEN4_2D:
- isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout,
- image_align_sa, phys_level0_sa,
- phys_slice0_sa);
+ isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout,
+ image_align_sa, phys_level0_sa,
+ array_pitch_span,
+ array_pitch_el_rows,
+ total_extent_el);
return;
- case ISL_DIM_LAYOUT_GEN4_3D:
- isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa,
- phys_level0_sa, phys_slice0_sa);
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
+ isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev, info, tile_info,
+ image_align_sa,
+ phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
return;
- }
-}
-
-/**
- * Calculate the pitch between physical array slices, in units of rows of
- * surface elements.
- */
-static uint32_t
-isl_calc_array_pitch_el_rows(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- const struct isl_tile_info *tile_info,
- enum isl_dim_layout dim_layout,
- enum isl_array_pitch_span array_pitch_span,
- const struct isl_extent3d *image_align_sa,
- const struct isl_extent4d *phys_level0_sa,
- const struct isl_extent2d *phys_slice0_sa)
-{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
- uint32_t pitch_sa_rows = 0;
-
- switch (dim_layout) {
- case ISL_DIM_LAYOUT_GEN9_1D:
- /* Each row is an array slice */
- pitch_sa_rows = 1;
- break;
- case ISL_DIM_LAYOUT_GEN4_2D:
- switch (array_pitch_span) {
- case ISL_ARRAY_PITCH_SPAN_COMPACT:
- pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
- break;
- case ISL_ARRAY_PITCH_SPAN_FULL: {
- /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
- * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
- * Surfaces >> Surface Arrays.
- */
- uint32_t H0_sa = phys_level0_sa->h;
- uint32_t H1_sa = isl_minify(H0_sa, 1);
-
- uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
- uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
-
- uint32_t m;
- if (ISL_DEV_GEN(dev) >= 7) {
- /* The QPitch equation changed slightly in Ivybridge. */
- m = 12;
- } else {
- m = 11;
- }
-
- pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
-
- if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
- (info->height % 4 == 1)) {
- /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
- * Graphics Core >> Section 7.18.3.7: Surface Arrays:
- *
- * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
- * the value calculated in the equation above , for every
- * other odd Surface Height starting from 1 i.e. 1,5,9,13.
- *
- * XXX(chadv): Is the errata natural corollary of the physical
- * layout of interleaved samples?
- */
- pitch_sa_rows += 4;
- }
-
- pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
- } /* end case */
- break;
- }
- break;
case ISL_DIM_LAYOUT_GEN4_3D:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
- pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
- break;
- default:
- unreachable("bad isl_dim_layout");
- break;
- }
-
- assert(pitch_sa_rows % fmtl->bh == 0);
- uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
-
- if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
- /*
- * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
- *
- * "Mip-mapped and arrayed surfaces are supported with MCS buffer
- * layout with these alignments in the RT space: Horizontal
- * Alignment = 128 and Vertical Alignment = 64."
- *
- * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
- *
- * "For non-multisampled render target's CCS auxiliary surface,
- * QPitch must be computed with Horizontal Alignment = 128 and
- * Surface Vertical Alignment = 256. These alignments are only for
- * CCS buffer and not for associated render target."
- *
- * The first restriction is already handled by isl_choose_image_alignment_el
- * but the second restriction, which is an extension of the first, only
- * applies to qpitch and must be applied here.
- */
- assert(fmtl->bh == 4);
- pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
- }
-
- if (ISL_DEV_GEN(dev) >= 9 &&
- info->dim == ISL_SURF_DIM_3D &&
- tile_info->tiling != ISL_TILING_LINEAR) {
- /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
- *
- * Tile Mode != Linear: This field must be set to an integer multiple
- * of the tile height
- */
- pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
+ isl_calc_phys_total_extent_el_gen4_3d(dev, info,
+ image_align_sa, phys_level0_sa,
+ array_pitch_el_rows,
+ total_extent_el);
+ return;
}
-
- return pitch_el_rows;
}
static uint32_t
static uint32_t
isl_calc_linear_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *info,
- const struct isl_extent2d *phys_slice0_sa,
+ const struct isl_extent2d *phys_total_el,
uint32_t alignment)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
const uint32_t bs = fmtl->bpb / 8;
- assert(phys_slice0_sa->w % fmtl->bw == 0);
-
- uint32_t min_row_pitch = bs * (phys_slice0_sa->w / fmtl->bw);
- min_row_pitch = MAX2(min_row_pitch, info->min_pitch);
- min_row_pitch = isl_align_npot(min_row_pitch, alignment);
-
- return min_row_pitch;
+ return isl_align_npot(bs * phys_total_el->w, alignment);
}
static uint32_t
isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
- const struct isl_extent2d *phys_slice0_sa,
+ const struct isl_extent2d *phys_total_el,
uint32_t alignment)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
assert(fmtl->bpb % tile_info->format_bpb == 0);
- assert(phys_slice0_sa->w % fmtl->bw == 0);
const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
- const uint32_t total_w_el = phys_slice0_sa->width / fmtl->bw;
const uint32_t total_w_tl =
- isl_align_div(total_w_el * tile_el_scale,
+ isl_align_div(phys_total_el->w * tile_el_scale,
tile_info->logical_extent_el.width);
- uint32_t min_row_pitch = total_w_tl * tile_info->phys_extent_B.width;
- min_row_pitch = MAX2(min_row_pitch, surf_info->min_pitch);
- min_row_pitch = isl_align_npot(min_row_pitch, alignment);
-
- return min_row_pitch;
+ assert(alignment == tile_info->phys_extent_B.width);
+ return total_w_tl * tile_info->phys_extent_B.width;
}
static uint32_t
isl_calc_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
- const struct isl_extent2d *phys_slice0_sa,
+ const struct isl_extent2d *phys_total_el,
uint32_t alignment)
{
if (tile_info->tiling == ISL_TILING_LINEAR) {
- return isl_calc_linear_min_row_pitch(dev, surf_info, phys_slice0_sa,
+ return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
alignment);
} else {
return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
- phys_slice0_sa, alignment);
+ phys_total_el, alignment);
}
}
-static uint32_t
+/**
+ * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
+ * size is `bits` bits?
+ *
+ * Hardware pitch fields are offset by 1. For example, if the size of
+ * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
+ * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
+ * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
+ */
+static bool
+pitch_in_range(uint32_t n, uint32_t bits)
+{
+ assert(n != 0);
+ return likely(bits != 0 && 1 <= n && n <= (1 << bits));
+}
+
+static bool
isl_calc_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
enum isl_dim_layout dim_layout,
- const struct isl_extent2d *phys_slice0_sa)
+ const struct isl_extent2d *phys_total_el,
+ uint32_t *out_row_pitch)
{
const uint32_t alignment =
isl_calc_row_pitch_alignment(surf_info, tile_info);
- return isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_slice0_sa,
- alignment);
+ const uint32_t min_row_pitch =
+ isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
+ alignment);
+
+ uint32_t row_pitch = min_row_pitch;
+
+ if (surf_info->row_pitch != 0) {
+ row_pitch = surf_info->row_pitch;
+
+ if (row_pitch < min_row_pitch)
+ return false;
+
+ if (row_pitch % alignment != 0)
+ return false;
+ }
+
+ const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width;
+
+ if (row_pitch == 0)
+ return false;
+
+ if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
+ /* SurfacePitch is ignored for this layout. */
+ goto done;
+ }
+
+ if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_STORAGE_BIT)) &&
+ !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
+ ISL_SURF_USAGE_MCS_BIT)) &&
+ !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
+ isl_finishme("validate row pitch of stencil surfaces");
+
+ done:
+ *out_row_pitch = row_pitch;
+ return true;
}
/**
return false;
struct isl_tile_info tile_info;
- if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, &tile_info))
- return false;
+ isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
const enum isl_dim_layout dim_layout =
isl_surf_choose_dim_layout(dev, info->dim, tiling);
enum isl_array_pitch_span array_pitch_span =
isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
- struct isl_extent2d phys_slice0_sa;
- isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout,
- &image_align_sa, &phys_level0_sa,
- &phys_slice0_sa);
- assert(phys_slice0_sa.w % fmtl->bw == 0);
- assert(phys_slice0_sa.h % fmtl->bh == 0);
-
- const uint32_t array_pitch_el_rows =
- isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout,
- array_pitch_span, &image_align_sa,
- &phys_level0_sa, &phys_slice0_sa);
-
- uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
+ uint32_t array_pitch_el_rows;
+ struct isl_extent2d phys_total_el;
+ isl_calc_phys_total_extent_el(dev, info, &tile_info,
+ dim_layout, msaa_layout,
+ &image_align_sa, &phys_level0_sa,
+ array_pitch_span, &array_pitch_el_rows,
+ &phys_total_el);
+ uint32_t padded_h_el = phys_total_el.h;
uint32_t pad_bytes;
- isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes);
+ isl_apply_surface_padding(dev, info, &tile_info, &padded_h_el, &pad_bytes);
- const uint32_t row_pitch = isl_calc_row_pitch(dev, info, &tile_info,
- dim_layout, &phys_slice0_sa);
+ uint32_t row_pitch;
+ if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
+ &phys_total_el, &row_pitch))
+ return false;
- uint32_t size, base_alignment;
+ uint32_t base_alignment;
+ uint64_t size;
if (tiling == ISL_TILING_LINEAR) {
- size = row_pitch * total_h_el + pad_bytes;
+ size = row_pitch * padded_h_el + pad_bytes;
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
*
}
base_alignment = isl_round_up_to_power_of_two(base_alignment);
} else {
- total_h_el += isl_align_div_npot(pad_bytes, row_pitch);
+ padded_h_el += isl_align_div_npot(pad_bytes, row_pitch);
const uint32_t total_h_tl =
- isl_align_div(total_h_el, tile_info.logical_extent_el.height);
+ isl_align_div(padded_h_el, tile_info.logical_extent_el.height);
size = total_h_tl * tile_info.phys_extent_B.height * row_pitch;
base_alignment = MAX(info->min_alignment, tile_size);
}
+ if (ISL_DEV_GEN(dev) < 9) {
+ /* From the Broadwell PRM Vol 5, Surface Layout:
+ *
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size in bytes. This
+ * maximum is 2 GB for all products and all surface types."
+ *
+ * This comment is applicable to all Pre-gen9 platforms.
+ */
+ if (size > (uint64_t) 1 << 31)
+ return false;
+ } else {
+ /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size of 2^38 bytes.
+ * All pixels within the surface must be contained within 2^38 bytes
+ * of the base address."
+ */
+ if (size > (uint64_t) 1 << 38)
+ return false;
+ }
+
*surf = (struct isl_surf) {
.dim = info->dim,
.dim_layout = dim_layout,
}
void
-isl_surf_get_tile_info(const struct isl_device *dev,
- const struct isl_surf *surf,
+isl_surf_get_tile_info(const struct isl_surf *surf,
struct isl_tile_info *tile_info)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info);
+ isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info);
}
bool
case 9:
isl_gen9_surf_fill_state_s(dev, state, info);
break;
+ case 10:
+ isl_gen10_surf_fill_state_s(dev, state, info);
+ break;
default:
assert(!"Cannot fill surface state for this gen");
}
case 9:
isl_gen9_buffer_fill_state_s(state, info);
break;
+ case 10:
+ isl_gen10_buffer_fill_state_s(state, info);
+ break;
+ default:
+ assert(!"Cannot fill surface state for this gen");
+ }
+}
+
+void
+isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+ const struct isl_depth_stencil_hiz_emit_info *restrict info)
+{
+ if (info->depth_surf && info->stencil_surf) {
+ if (!dev->info->has_hiz_and_separate_stencil) {
+ assert(info->depth_surf == info->stencil_surf);
+ assert(info->depth_address == info->stencil_address);
+ }
+ assert(info->depth_surf->dim == info->stencil_surf->dim);
+ }
+
+ if (info->depth_surf) {
+ assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
+ if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.depth);
+ } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.array_len);
+ }
+ }
+
+ if (info->stencil_surf) {
+ assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
+ if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.depth);
+ } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.array_len);
+ }
+ }
+
+ switch (ISL_DEV_GEN(dev)) {
+ case 4:
+ if (ISL_DEV_IS_G4X(dev)) {
+ /* G45 surface state is the same as gen5 */
+ isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+ } else {
+ isl_gen4_emit_depth_stencil_hiz_s(dev, batch, info);
+ }
+ break;
+ case 5:
+ isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 6:
+ isl_gen6_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 7:
+ if (ISL_DEV_IS_HASWELL(dev)) {
+ isl_gen75_emit_depth_stencil_hiz_s(dev, batch, info);
+ } else {
+ isl_gen7_emit_depth_stencil_hiz_s(dev, batch, info);
+ }
+ break;
+ case 8:
+ isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 9:
+ isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 10:
+ isl_gen10_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
default:
assert(!"Cannot fill surface state for this gen");
}
uint32_t *y_offset_sa)
{
assert(level < surf->levels);
- assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
- assert(surf->phys_level0_sa.array_len == 1);
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ assert(surf->phys_level0_sa.array_len == 1);
+ assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
+ } else {
+ assert(surf->dim == ISL_SURF_DIM_2D);
+ assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
+ assert(surf->phys_level0_sa.array_len == 6);
+ assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
+ }
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
const uint32_t W0 = surf->phys_level0_sa.width;
const uint32_t H0 = surf->phys_level0_sa.height;
const uint32_t D0 = surf->phys_level0_sa.depth;
+ const uint32_t AL = surf->phys_level0_sa.array_len;
uint32_t x = 0;
uint32_t y = 0;
for (uint32_t l = 0; l < level; ++l) {
const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
+ image_align_sa.d);
const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
y += level_h * max_layers_vert;
const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
+ image_align_sa.d);
const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
*y_offset_sa = y;
}
+static void
+get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+ assert(level < surf->levels);
+ assert(surf->logical_level0_px.depth == 1);
+ assert(logical_array_layer < surf->logical_level0_px.array_len);
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ const struct isl_extent3d image_align_sa =
+ isl_surf_get_image_alignment_sa(surf);
+
+ struct isl_tile_info tile_info;
+ isl_tiling_get_info(surf->tiling, fmtl->bpb, &tile_info);
+ const struct isl_extent2d tile_extent_sa = {
+ .w = tile_info.logical_extent_el.w * fmtl->bw,
+ .h = tile_info.logical_extent_el.h * fmtl->bh,
+ };
+ /* Tile size is a multiple of image alignment */
+ assert(tile_extent_sa.w % image_align_sa.w == 0);
+ assert(tile_extent_sa.h % image_align_sa.h == 0);
+
+ const uint32_t W0 = surf->phys_level0_sa.w;
+ const uint32_t H0 = surf->phys_level0_sa.h;
+
+ /* Each image has the same height as LOD0 because the hardware thinks
+ * everything is LOD0
+ */
+ const uint32_t H = isl_align(H0, image_align_sa.h);
+
+ /* Quick sanity check for consistency */
+ if (surf->phys_level0_sa.array_len > 1)
+ assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
+
+ uint32_t x = 0, y = 0;
+ for (uint32_t l = 0; l < level; ++l) {
+ const uint32_t W = isl_minify(W0, l);
+
+ const uint32_t w = isl_align(W, tile_extent_sa.w);
+ const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
+ tile_extent_sa.h);
+
+ if (l == 0) {
+ y += h;
+ } else {
+ x += w;
+ }
+ }
+
+ y += H * logical_array_layer;
+
+ *x_offset_sa = x;
+ *y_offset_sa = y;
+}
+
/**
* A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN9_1D.
x_offset_sa, y_offset_sa);
break;
case ISL_DIM_LAYOUT_GEN4_3D:
- get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px,
+ get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
+ logical_z_offset_px,
x_offset_sa, y_offset_sa);
break;
+ case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
+ get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer +
+ logical_z_offset_px,
+ x_offset_sa, y_offset_sa);
+ break;
default:
unreachable("not reached");
}
void
-isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
- enum isl_tiling tiling,
- uint8_t bs,
+isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ uint32_t *offset_B,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ uint32_t total_x_offset_el, total_y_offset_el;
+ isl_surf_get_image_offset_el(surf, level, logical_array_layer,
+ logical_z_offset_px,
+ &total_x_offset_el,
+ &total_y_offset_el);
+
+ uint32_t x_offset_el, y_offset_el;
+ isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
+ surf->row_pitch,
+ total_x_offset_el,
+ total_y_offset_el,
+ offset_B,
+ &x_offset_el,
+ &y_offset_el);
+
+ if (x_offset_sa) {
+ *x_offset_sa = x_offset_el * fmtl->bw;
+ } else {
+ assert(x_offset_el == 0);
+ }
+
+ if (y_offset_sa) {
+ *y_offset_sa = y_offset_el * fmtl->bh;
+ } else {
+ assert(y_offset_el == 0);
+ }
+}
+
+void
+isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
+ uint32_t bpb,
uint32_t row_pitch,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *y_offset_el)
{
if (tiling == ISL_TILING_LINEAR) {
+ assert(bpb % 8 == 0);
*base_address_offset = total_y_offset_el * row_pitch +
- total_x_offset_el * bs;
+ total_x_offset_el * (bpb / 8);
*x_offset_el = 0;
*y_offset_el = 0;
return;
}
- const uint32_t bpb = bs * 8;
-
struct isl_tile_info tile_info;
- isl_tiling_get_info(dev, tiling, bpb, &tile_info);
+ isl_tiling_get_info(tiling, bpb, &tile_info);
assert(row_pitch % tile_info.phys_extent_B.width == 0);
projects / mesa.git / blobdiff