if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY)
return false;
+ if (mcs_surf->size_B > 0)
+ return false;
+
/* The following are true of all multisampled surfaces */
assert(surf->samples > 1);
assert(surf->dim == ISL_SURF_DIM_2D);
if (aux_surf->usage & ISL_SURF_USAGE_CCS_BIT)
return false;
- /* Only multisampled depth buffers with HiZ can have CCS. */
- if (surf->samples > 1 && !(aux_surf->usage & ISL_SURF_USAGE_HIZ_BIT))
+ if (ISL_DEV_GEN(dev) < 12 && surf->samples > 1)
return false;
- assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
- surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
-
/* CCS support does not exist prior to Gen7 */
if (ISL_DEV_GEN(dev) <= 6)
return false;
if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
return false;
- /* Callers don't yet support this configuration. */
- if (isl_surf_usage_is_stencil(surf->usage))
+ /* Allow CCS for single-sampled stencil buffers Gen12+. */
+ if (isl_surf_usage_is_stencil(surf->usage) &&
+ (ISL_DEV_GEN(dev) < 12 || surf->samples > 1))
return false;
/* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if it
}
}
+bool
+isl_surf_supports_hiz_ccs_wt(const struct gen_device_info *dev,
+ const struct isl_surf *surf,
+ enum isl_aux_usage aux_usage)
+{
+ return aux_usage == ISL_AUX_USAGE_HIZ_CCS &&
+ surf->samples == 1 &&
+ surf->usage & ISL_SURF_USAGE_TEXTURE_BIT;
+}
+
bool
isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
struct isl_swizzle swizzle)