intel/isl: Resize clear color buffer to full cacheline

[mesa.git] / src / intel / isl / isl.c

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6b9e6c9e0f02ed2e84e32f28cc7c868a61704101..acfed5119ba97bcfdcdfcbf23232dc9d8a4cb973 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -122,7 +122,8 @@ isl_device_init(struct isl_device *dev,
    dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
    dev->ss.align = isl_align(dev->ss.size, 32);
 
-   dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
+   dev->ss.clear_color_state_size =
+      isl_align(CLEAR_COLOR_length(info) * 4, 64);
    dev->ss.clear_color_state_offset =
       RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;