#include <stdarg.h>
#include <stdio.h>
+#include "genxml/genX_bits.h"
+
#include "isl.h"
#include "isl_gen4.h"
#include "isl_gen6.h"
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
}
-static const struct {
- uint8_t size;
- uint8_t align;
- uint8_t addr_offset;
- uint8_t aux_addr_offset;
-} ss_infos[] = {
- [4] = {24, 32, 4},
- [5] = {24, 32, 4},
- [6] = {24, 32, 4},
- [7] = {32, 32, 4, 24},
- [8] = {52, 64, 32, 40},
- [9] = {64, 64, 32, 40},
-};
-
void
isl_device_init(struct isl_device *dev,
const struct gen_device_info *info,
if (info->must_use_separate_stencil)
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
- dev->ss.size = ss_infos[ISL_DEV_GEN(dev)].size;
- dev->ss.align = ss_infos[ISL_DEV_GEN(dev)].align;
- dev->ss.addr_offset = ss_infos[ISL_DEV_GEN(dev)].addr_offset;
- dev->ss.aux_addr_offset = ss_infos[ISL_DEV_GEN(dev)].aux_addr_offset;
+ dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
+ dev->ss.align = isl_align(dev->ss.size, 32);
+
+ assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ss.addr_offset =
+ RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
+
+ /* The "Auxiliary Surface Base Address" field starts a bit higher up
+ * because the bottom 12 bits are used for other things. Round down to
+ * the nearest dword before.
+ */
+ dev->ss.aux_addr_offset =
+ (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
+
+ dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
+ assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.depth_offset =
+ _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ if (dev->use_separate_stencil) {
+ dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_CLEAR_PARAMS_length(info) * 4;
+
+ assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.stencil_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+ assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+ dev->ds.hiz_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+ } else {
+ dev->ds.stencil_offset = 0;
+ dev->ds.hiz_offset = 0;
+ }
}
/**
/**
* @param[out] info is written only on success
*/
-static bool
-isl_tiling_get_info(const struct isl_device *dev,
- enum isl_tiling tiling,
+static void
+isl_tiling_get_info(enum isl_tiling tiling,
uint32_t format_bpb,
struct isl_tile_info *tile_info)
{
*/
assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
- return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info);
+ isl_tiling_get_info(tiling, format_bpb / 3, tile_info);
+ return;
}
switch (tiling) {
case ISL_TILING_Yf:
case ISL_TILING_Ys: {
- if (ISL_DEV_GEN(dev) < 9)
- return false;
-
- if (!isl_is_pow2(bs))
- return false;
-
bool is_Ys = tiling == ISL_TILING_Ys;
assert(bs > 0);
.logical_extent_el = logical_el,
.phys_extent_B = phys_B,
};
-
- return true;
}
/**
if (ISL_DEV_GEN(dev) >= 6) {
isl_gen6_filter_tiling(dev, info, &tiling_flags);
} else {
- isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
- isl_gen6_filter_tiling(dev, info, &tiling_flags);
+ isl_gen4_filter_tiling(dev, info, &tiling_flags);
}
#define CHOOSE(__tiling) \
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el)
{
- if (info->format == ISL_FORMAT_HIZ) {
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ if (fmtl->txc == ISL_TXC_MCS) {
+ assert(tiling == ISL_TILING_Y0);
+
+ /*
+ * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
+ *
+ * Height, width, and layout of MCS buffer in this case must match with
+ * Render Target height, width, and layout. MCS buffer is tiledY.
+ *
+ * To avoid wasting memory, choose the smallest alignment possible:
+ * HALIGN_4 and VALIGN_4.
+ */
+ *image_align_el = isl_extent3d(4, 4, 1);
+ return;
+ } else if (info->format == ISL_FORMAT_HIZ) {
assert(ISL_DEV_GEN(dev) >= 6);
/* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
* which works out to 2x2 HiZ elments.
return pitch_el_rows;
}
-/**
- * Calculate the pitch of each surface row, in bytes.
- */
static uint32_t
-isl_calc_linear_row_pitch(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict info,
- const struct isl_extent2d *phys_slice0_sa)
+isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info)
{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
- uint32_t row_pitch = info->min_pitch;
-
- /* First, align the surface to a cache line boundary, as the PRM explains
- * below.
- *
- * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Render Target and Media
- * Surfaces:
- *
- * The data port accesses data (pixels) outside of the surface if they
- * are contained in the same cache request as pixels that are within the
- * surface. These pixels will not be returned by the requesting message,
- * however if these pixels lie outside of defined pages in the GTT,
- * a GTT error will result when the cache request is processed. In order
- * to avoid these GTT errors, “padding” at the bottom of the surface is
- * sometimes necessary.
- *
- * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
- * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
- *
- * The sampling engine accesses texels outside of the surface if they
- * are contained in the same cache line as texels that are within the
- * surface. These texels will not participate in any calculation
- * performed by the sampling engine and will not affect the result of
- * any sampling engine operation, however if these texels lie outside of
- * defined pages in the GTT, a GTT error will result when the cache line
- * is accessed. In order to avoid these GTT errors, “padding” at the
- * bottom and right side of a sampling engine surface is sometimes
- * necessary.
- *
- * It is possible that a cache line will straddle a page boundary if the
- * base address or pitch is not aligned. All pages included in the cache
- * lines that are part of the surface must map to valid GTT entries to
- * avoid errors. To determine the necessary padding on the bottom and
- * right side of the surface, refer to the table in Alignment Unit Size
- * section for the i and j parameters for the surface format in use. The
- * surface must then be extended to the next multiple of the alignment
- * unit size in each dimension, and all texels contained in this
- * extended surface must have valid GTT entries.
- *
- * For example, suppose the surface size is 15 texels by 10 texels and
- * the alignment parameters are i=4 and j=2. In this case, the extended
- * surface would be 16 by 10. Note that these calculations are done in
- * texels, and must be converted to bytes based on the surface format
- * being used to determine whether additional pages need to be defined.
- */
- assert(phys_slice0_sa->w % fmtl->bw == 0);
- const uint32_t bs = fmtl->bpb / 8;
- row_pitch = MAX(row_pitch, bs * (phys_slice0_sa->w / fmtl->bw));
+ if (tile_info->tiling != ISL_TILING_LINEAR)
+ return tile_info->phys_extent_B.width;
/* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
* RENDER_SURFACE_STATE Surface Pitch (p349):
* - For other linear surfaces, the pitch can be any multiple of
* bytes.
*/
- if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
- if (isl_format_is_yuv(info->format)) {
- row_pitch = isl_align_npot(row_pitch, 2 * bs);
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
+ const uint32_t bs = fmtl->bpb / 8;
+
+ if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
+ if (isl_format_is_yuv(surf_info->format)) {
+ return 2 * bs;
} else {
- row_pitch = isl_align_npot(row_pitch, bs);
+ return bs;
}
}
- return row_pitch;
+ return 1;
+}
+
+static uint32_t
+isl_calc_linear_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *info,
+ const struct isl_extent2d *phys_slice0_sa,
+ uint32_t alignment)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+ const uint32_t bs = fmtl->bpb / 8;
+
+ assert(phys_slice0_sa->w % fmtl->bw == 0);
+
+ return isl_align_npot(bs * (phys_slice0_sa->w / fmtl->bw), alignment);
+}
+
+static uint32_t
+isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent2d *phys_slice0_sa,
+ uint32_t alignment)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
+
+ assert(fmtl->bpb % tile_info->format_bpb == 0);
+ assert(phys_slice0_sa->w % fmtl->bw == 0);
+
+ const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
+ const uint32_t total_w_el = phys_slice0_sa->width / fmtl->bw;
+ const uint32_t total_w_tl =
+ isl_align_div(total_w_el * tile_el_scale,
+ tile_info->logical_extent_el.width);
+
+ assert(alignment == tile_info->phys_extent_B.width);
+ return total_w_tl * tile_info->phys_extent_B.width;
+}
+
+static uint32_t
+isl_calc_min_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ const struct isl_extent2d *phys_slice0_sa,
+ uint32_t alignment)
+{
+ if (tile_info->tiling == ISL_TILING_LINEAR) {
+ return isl_calc_linear_min_row_pitch(dev, surf_info, phys_slice0_sa,
+ alignment);
+ } else {
+ return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
+ phys_slice0_sa, alignment);
+ }
+}
+
+/**
+ * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
+ * size is `bits` bits?
+ *
+ * Hardware pitch fields are offset by 1. For example, if the size of
+ * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
+ * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
+ * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
+ */
+static bool
+pitch_in_range(uint32_t n, uint32_t bits)
+{
+ assert(n != 0);
+ return likely(bits != 0 && 1 <= n && n <= (1 << bits));
+}
+
+static bool
+isl_calc_row_pitch(const struct isl_device *dev,
+ const struct isl_surf_init_info *surf_info,
+ const struct isl_tile_info *tile_info,
+ enum isl_dim_layout dim_layout,
+ const struct isl_extent2d *phys_slice0_sa,
+ uint32_t *out_row_pitch)
+{
+ const uint32_t alignment =
+ isl_calc_row_pitch_alignment(surf_info, tile_info);
+
+ const uint32_t min_row_pitch =
+ isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_slice0_sa,
+ alignment);
+
+ uint32_t row_pitch = min_row_pitch;
+
+ if (surf_info->row_pitch != 0) {
+ row_pitch = surf_info->row_pitch;
+
+ if (row_pitch < min_row_pitch)
+ return false;
+
+ if (row_pitch % alignment != 0)
+ return false;
+ }
+
+ const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width;
+
+ if (row_pitch == 0)
+ return false;
+
+ if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
+ /* SurfacePitch is ignored for this layout. */
+ goto done;
+ }
+
+ if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_STORAGE_BIT)) &&
+ !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
+ ISL_SURF_USAGE_MCS_BIT)) &&
+ !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
+ !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
+ return false;
+
+ if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
+ isl_finishme("validate row pitch of stencil surfaces");
+
+ done:
+ *out_row_pitch = row_pitch;
+ return true;
}
/**
return false;
struct isl_tile_info tile_info;
- if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, &tile_info))
- return false;
+ isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
const enum isl_dim_layout dim_layout =
isl_surf_choose_dim_layout(dev, info->dim, tiling);
uint32_t pad_bytes;
isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes);
- uint32_t row_pitch, size, base_alignment;
+ uint32_t row_pitch;
+ if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
+ &phys_slice0_sa, &row_pitch))
+ return false;
+
+ uint32_t size, base_alignment;
if (tiling == ISL_TILING_LINEAR) {
- row_pitch = isl_calc_linear_row_pitch(dev, info, &phys_slice0_sa);
size = row_pitch * total_h_el + pad_bytes;
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
}
base_alignment = isl_round_up_to_power_of_two(base_alignment);
} else {
- assert(fmtl->bpb % tile_info.format_bpb == 0);
- const uint32_t tile_el_scale = fmtl->bpb / tile_info.format_bpb;
-
- assert(phys_slice0_sa.w % fmtl->bw == 0);
- const uint32_t total_w_el = phys_slice0_sa.width / fmtl->bw;
- const uint32_t total_w_tl =
- isl_align_div(total_w_el * tile_el_scale,
- tile_info.logical_extent_el.width);
-
- row_pitch = total_w_tl * tile_info.phys_extent_B.width;
- if (row_pitch < info->min_pitch) {
- row_pitch = isl_align_npot(info->min_pitch,
- tile_info.phys_extent_B.width);
- }
-
total_h_el += isl_align_div_npot(pad_bytes, row_pitch);
const uint32_t total_h_tl =
isl_align_div(total_h_el, tile_info.logical_extent_el.height);
}
void
-isl_surf_get_tile_info(const struct isl_device *dev,
- const struct isl_surf *surf,
+isl_surf_get_tile_info(const struct isl_surf *surf,
struct isl_tile_info *tile_info)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info);
+ isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info);
}
bool
assert(surf->levels == 1);
assert(surf->logical_level0_px.depth == 1);
+ /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
+ * bits which means the maximum pitch of a compression surface is 512
+ * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
+ * 64bpp, this gives us a maximum width of 8192 pixels. We can create
+ * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
+ * and 8x, we have enough room for the full 16k supported by the hardware.
+ */
+ if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
+ return false;
+
enum isl_format mcs_format;
switch (surf->samples) {
case 2: mcs_format = ISL_FORMAT_MCS_2X; break;
}
}
+void
+isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+ const struct isl_depth_stencil_hiz_emit_info *restrict info)
+{
+ if (info->depth_surf && info->stencil_surf) {
+ if (!dev->info->has_hiz_and_separate_stencil) {
+ assert(info->depth_surf == info->stencil_surf);
+ assert(info->depth_address == info->stencil_address);
+ }
+ assert(info->depth_surf->dim == info->stencil_surf->dim);
+ }
+
+ if (info->depth_surf) {
+ assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
+ if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.depth);
+ } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->depth_surf->logical_level0_px.array_len);
+ }
+ }
+
+ if (info->stencil_surf) {
+ assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
+ if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.depth);
+ } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+ info->stencil_surf->logical_level0_px.array_len);
+ }
+ }
+
+ switch (ISL_DEV_GEN(dev)) {
+ case 4:
+ if (ISL_DEV_IS_G4X(dev)) {
+ /* G45 surface state is the same as gen5 */
+ isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+ } else {
+ isl_gen4_emit_depth_stencil_hiz_s(dev, batch, info);
+ }
+ break;
+ case 5:
+ isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 6:
+ isl_gen6_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 7:
+ if (ISL_DEV_IS_HASWELL(dev)) {
+ isl_gen75_emit_depth_stencil_hiz_s(dev, batch, info);
+ } else {
+ isl_gen7_emit_depth_stencil_hiz_s(dev, batch, info);
+ }
+ break;
+ case 8:
+ isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ case 9:
+ isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
+ break;
+ default:
+ assert(!"Cannot fill surface state for this gen");
+ }
+}
+
/**
* A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN4_2D.
uint32_t *y_offset_sa)
{
assert(level < surf->levels);
- assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
- assert(surf->phys_level0_sa.array_len == 1);
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ assert(surf->phys_level0_sa.array_len == 1);
+ assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
+ } else {
+ assert(surf->dim == ISL_SURF_DIM_2D);
+ assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
+ assert(surf->phys_level0_sa.array_len == 6);
+ assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
+ }
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
const uint32_t W0 = surf->phys_level0_sa.width;
const uint32_t H0 = surf->phys_level0_sa.height;
const uint32_t D0 = surf->phys_level0_sa.depth;
+ const uint32_t AL = surf->phys_level0_sa.array_len;
uint32_t x = 0;
uint32_t y = 0;
for (uint32_t l = 0; l < level; ++l) {
const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
+ image_align_sa.d);
const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
y += level_h * max_layers_vert;
const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
- const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d);
+ const uint32_t level_d =
+ isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
+ image_align_sa.d);
const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
x_offset_sa, y_offset_sa);
break;
case ISL_DIM_LAYOUT_GEN4_3D:
- get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px,
+ get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
+ logical_z_offset_px,
x_offset_sa, y_offset_sa);
break;
}
void
-isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
- enum isl_tiling tiling,
+isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint8_t bs,
uint32_t row_pitch,
uint32_t total_x_offset_el,
const uint32_t bpb = bs * 8;
struct isl_tile_info tile_info;
- isl_tiling_get_info(dev, tiling, bpb, &tile_info);
+ isl_tiling_get_info(tiling, bpb, &tile_info);
assert(row_pitch % tile_info.phys_extent_B.width == 0);
projects / mesa.git / blobdiff