intel/isl: Remove the device parameter from isl_tiling_get_info

[mesa.git] / src / intel / isl / isl.c

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351c15771c3fc087a2a22b03e5af24450b2b..f0e948a1c9648eeef88aed1f26f528225c82f211 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -84,17 +84,16 @@ isl_device_init(struct isl_device *dev,
    dev->ss.aux_addr_offset =
       (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
 
-   dev->ds.size =
-      _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
-      _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
-      _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
-      _3DSTATE_CLEAR_PARAMS_length(info) * 4;
-
+   dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
    assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
    dev->ds.depth_offset =
       _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
 
-   if (info->has_hiz_and_separate_stencil) {
+   if (dev->use_separate_stencil) {
+      dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+                      _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
+                      _3DSTATE_CLEAR_PARAMS_length(info) * 4;
+
       assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
       dev->ds.stencil_offset =
          _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
@@ -146,9 +145,8 @@ isl_device_get_sample_counts(struct isl_device *dev)
 /**
  * @param[out] info is written only on success
  */
-static bool
-isl_tiling_get_info(const struct isl_device *dev,
-                    enum isl_tiling tiling,
+static void
+isl_tiling_get_info(enum isl_tiling tiling,
                     uint32_t format_bpb,
                     struct isl_tile_info *tile_info)
 {
@@ -163,7 +161,8 @@ isl_tiling_get_info(const struct isl_device *dev,
        */
       assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
       assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
-      return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info);
+      isl_tiling_get_info(tiling, format_bpb / 3, tile_info);
+      return;
    }
 
    switch (tiling) {
@@ -204,12 +203,6 @@ isl_tiling_get_info(const struct isl_device *dev,
 
    case ISL_TILING_Yf:
    case ISL_TILING_Ys: {
-      if (ISL_DEV_GEN(dev) < 9)
-         return false;
-
-      if (!isl_is_pow2(bs))
-         return false;
-
       bool is_Ys = tiling == ISL_TILING_Ys;
 
       assert(bs > 0);
@@ -264,8 +257,6 @@ isl_tiling_get_info(const struct isl_device *dev,
       .logical_extent_el = logical_el,
       .phys_extent_B = phys_B,
    };
-
-   return true;
 }
 
 /**
@@ -297,8 +288,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
    if (ISL_DEV_GEN(dev) >= 6) {
       isl_gen6_filter_tiling(dev, info, &tiling_flags);
    } else {
-      isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
-      isl_gen6_filter_tiling(dev, info, &tiling_flags);
+      isl_gen4_filter_tiling(dev, info, &tiling_flags);
    }
 
    #define CHOOSE(__tiling) \
@@ -1314,8 +1304,7 @@ isl_surf_init_s(const struct isl_device *dev,
       return false;
 
    struct isl_tile_info tile_info;
-   if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, &tile_info))
-      return false;
+   isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
 
    const enum isl_dim_layout dim_layout =
       isl_surf_choose_dim_layout(dev, info->dim, tiling);
@@ -1424,12 +1413,11 @@ isl_surf_init_s(const struct isl_device *dev,
 }
 
 void
-isl_surf_get_tile_info(const struct isl_device *dev,
-                       const struct isl_surf *surf,
+isl_surf_get_tile_info(const struct isl_surf *surf,
                        struct isl_tile_info *tile_info)
 {
    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
-   isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info);
+   isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info);
 }
 
 bool
@@ -1830,8 +1818,15 @@ get_image_offset_sa_gen4_3d(const struct isl_surf *surf,
                             uint32_t *y_offset_sa)
 {
    assert(level < surf->levels);
-   assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
-   assert(surf->phys_level0_sa.array_len == 1);
+   if (surf->dim == ISL_SURF_DIM_3D) {
+      assert(surf->phys_level0_sa.array_len == 1);
+      assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
+   } else {
+      assert(surf->dim == ISL_SURF_DIM_2D);
+      assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
+      assert(surf->phys_level0_sa.array_len == 6);
+      assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
+   }
 
    const struct isl_extent3d image_align_sa =
       isl_surf_get_image_alignment_sa(surf);
@@ -1839,13 +1834,16 @@ get_image_offset_sa_gen4_3d(const struct isl_surf *surf,
    const uint32_t W0 = surf->phys_level0_sa.width;
    const uint32_t H0 = surf->phys_level0_sa.height;
    const uint32_t D0 = surf->phys_level0_sa.depth;
+   const uint32_t AL = surf->phys_level0_sa.array_len;
 
    uint32_t x = 0;
    uint32_t y = 0;
 
    for (uint32_t l = 0; l < level; ++l) {
       const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
-      const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d);
+      const uint32_t level_d =
+         isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
+                        image_align_sa.d);
       const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
 
       y += level_h * max_layers_vert;
@@ -1853,7 +1851,9 @@ get_image_offset_sa_gen4_3d(const struct isl_surf *surf,
 
    const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
    const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
-   const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d);
+   const uint32_t level_d =
+      isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
+                     image_align_sa.d);
 
    const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
 
@@ -1929,7 +1929,8 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf,
                                   x_offset_sa, y_offset_sa);
       break;
    case ISL_DIM_LAYOUT_GEN4_3D:
-      get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px,
+      get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
+                                  logical_z_offset_px,
                                   x_offset_sa, y_offset_sa);
       break;
 
@@ -1965,8 +1966,7 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf,
 }
 
 void
-isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
-                                   enum isl_tiling tiling,
+isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
                                    uint8_t bs,
                                    uint32_t row_pitch,
                                    uint32_t total_x_offset_el,
@@ -1986,7 +1986,7 @@ isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
    const uint32_t bpb = bs * 8;
 
    struct isl_tile_info tile_info;
-   isl_tiling_get_info(dev, tiling, bpb, &tile_info);
+   isl_tiling_get_info(tiling, bpb, &tile_info);
 
    assert(row_pitch % tile_info.phys_extent_B.width == 0);