ISL_FORMAT_GEN9_CCS_64BPP,
ISL_FORMAT_GEN9_CCS_128BPP,
+ /* An upper bound on the supported format enumerations */
+ ISL_NUM_FORMATS,
+
/* Hardware doesn't understand this out-of-band value */
ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
};
*
* Drawing with or without aux enabled may implicitly cause the surface to
* transition between these states. There are also four types of auxiliary
- * compression operations which cause an explicit transition:
- *
- * 1) Fast Clear: This operation writes the magic "clear" value to the
- * auxiliary surface. This operation will safely transition any slice
- * of a surface from any state to the clear state so long as the entire
- * slice is fast cleared at once. A fast clear that only covers part of
- * a slice of a surface is called a partial fast clear.
- *
- * 2) Full Resolve: This operation combines the auxiliary surface data
- * with the primary surface data and writes the result to the primary.
- * For HiZ, the docs call this a depth resolve. For CCS, the hardware
- * full resolve operation does both a full resolve and an ambiguate so
- * it actually takes you all the way to the pass-through state.
- *
- * 3) Partial Resolve: This operation considers blocks which are in the
- * "clear" state and writes the clear value directly into the primary or
- * auxiliary surface. Once this operation completes, the surface is
- * still compressed but no longer references the clear color. This
- * operation is only available for CCS.
- *
- * 4) Ambiguate: This operation throws away the current auxiliary data and
- * replaces it with the magic pass-through value. If an ambiguate
- * operation is performed when the primary surface does not contain 100%
- * of the data, data will be lost. This operation is only implemented
- * in hardware for depth where it is called a HiZ resolve.
+ * compression operations which cause an explicit transition which are
+ * described by the isl_aux_op enum below.
*
* Not all operations are valid or useful in all states. The diagram below
* contains a complete description of the states and all valid and useful
ISL_AUX_STATE_AUX_INVALID,
};
+/**
+ * Enum which describes explicit aux transition operations.
+ */
+enum isl_aux_op {
+ ISL_AUX_OP_NONE,
+
+ /** Fast Clear
+ *
+ * This operation writes the magic "clear" value to the auxiliary surface.
+ * This operation will safely transition any slice of a surface from any
+ * state to the clear state so long as the entire slice is fast cleared at
+ * once. A fast clear that only covers part of a slice of a surface is
+ * called a partial fast clear.
+ */
+ ISL_AUX_OP_FAST_CLEAR,
+
+ /** Full Resolve
+ *
+ * This operation combines the auxiliary surface data with the primary
+ * surface data and writes the result to the primary. For HiZ, the docs
+ * call this a depth resolve. For CCS, the hardware full resolve operation
+ * does both a full resolve and an ambiguate so it actually takes you all
+ * the way to the pass-through state.
+ */
+ ISL_AUX_OP_FULL_RESOLVE,
+
+ /** Partial Resolve
+ *
+ * This operation considers blocks which are in the "clear" state and
+ * writes the clear value directly into the primary or auxiliary surface.
+ * Once this operation completes, the surface is still compressed but no
+ * longer references the clear color. This operation is only available
+ * for CCS_E.
+ */
+ ISL_AUX_OP_PARTIAL_RESOLVE,
+
+ /** Ambiguate
+ *
+ * This operation throws away the current auxiliary data and replaces it
+ * with the magic pass-through value. If an ambiguate operation is
+ * performed when the primary surface does not contain 100% of the data,
+ * data will be lost. This operation is only implemented in hardware for
+ * depth where it is called a HiZ resolve.
+ */
+ ISL_AUX_OP_AMBIGUATE,
+};
+
/* TODO(chadv): Explain */
enum isl_array_pitch_span {
ISL_ARRAY_PITCH_SPAN_FULL,
uint8_t aux_addr_offset;
/* Rounded up to the nearest dword to simplify GPU memcpy operations. */
+
+ /* size of the state buffer used to store the clear color + extra
+ * additional space used by the hardware */
+ uint8_t clear_color_state_size;
+ uint8_t clear_color_state_offset;
+ /* size of the clear color itself - used to copy it to/from a BO */
uint8_t clear_value_size;
uint8_t clear_value_offset;
} ss;
struct isl_channel_layout {
enum isl_base_type type;
+ uint8_t start_bit; /**< Bit at which this channel starts */
uint8_t bits; /**< Size in bits */
};
* always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
* its physical size is 128B x 32rows, the same as a Y-tile.
*
- * @see isl_surf::row_pitch
+ * @see isl_surf::row_pitch_B
*/
struct isl_extent2d phys_extent_B;
};
uint32_t samples;
/** Lower bound for isl_surf::alignment, in bytes. */
- uint32_t min_alignment;
+ uint32_t min_alignment_B;
/**
* Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
* will fail if this is misaligned or out of bounds.
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
isl_surf_usage_flags_t usage;
uint32_t samples;
/** Total size of the surface, in bytes. */
- uint64_t size;
+ uint64_t size_B;
/** Required alignment for the surface's base address. */
- uint32_t alignment;
+ uint32_t alignment_B;
/**
* The interpretation of this field depends on the value of
* isl_tile_info::physical_extent_B. In particular, the width of the
- * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
+ * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
* and the distance in bytes between vertically adjacent tiles in the image
- * is given by row_pitch * isl_tile_info::physical_extent_B.height.
+ * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
*
* For linear images where isl_tile_info::physical_extent_B.height == 1,
* this cleanly reduces to being the distance, in bytes, between vertically
*
* @see isl_tile_info::phys_extent_B;
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
/**
* Pitch between physical array slices, in rows of surface elements.
*/
union isl_color_value clear_color;
+ /**
+ * Send only the clear value address
+ *
+ * If set, we only pass the clear address to the GPU and it will fetch it
+ * from wherever it is.
+ */
+ bool use_clear_address;
+ uint64_t clear_address;
+
/**
* Surface write disables for gen4-5
*/
/**
* The size of the buffer
*/
- uint64_t size;
+ uint64_t size_B;
/**
* The Memory Object Control state for the filled surface state.
*/
enum isl_format format;
- uint32_t stride;
+ uint32_t stride_B;
};
struct isl_depth_stencil_hiz_emit_info {
static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)
{
+ assert(fmt != ISL_FORMAT_UNSUPPORTED);
+ assert(fmt < ISL_NUM_FORMATS);
return &isl_format_layouts[fmt];
}
+bool isl_format_is_valid(enum isl_format);
+
static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)
{
- return isl_format_layouts[fmt].name;
+ return isl_format_get_layout(fmt)->name;
}
bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
static inline bool
isl_format_is_srgb(enum isl_format fmt)
{
- return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
+ return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
}
enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
static inline bool
isl_format_is_rgb(enum isl_format fmt)
{
- return isl_format_layouts[fmt].channels.r.bits > 0 &&
- isl_format_layouts[fmt].channels.g.bits > 0 &&
- isl_format_layouts[fmt].channels.b.bits > 0 &&
- isl_format_layouts[fmt].channels.a.bits == 0;
+ if (isl_format_is_yuv(fmt))
+ return false;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits == 0;
+}
+
+static inline bool
+isl_format_is_rgbx(enum isl_format fmt)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits > 0 &&
+ fmtl->channels.a.type == ISL_VOID;
}
enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
+enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
+
+void isl_color_value_pack(const union isl_color_value *value,
+ enum isl_format format,
+ uint32_t *data_out);
+void isl_color_value_unpack(union isl_color_value *value,
+ enum isl_format format,
+ const uint32_t *data_in);
bool isl_is_storage_image_format(enum isl_format fmt);
/** Returns the default isl_aux_state for the given modifier.
*
- * All modified images are required to be kept out of the AUX_INVALID state
- * but they may or may not actually be compressed and may or may not have
- * clear color. This function returns the worst case aux_state that we need
- * to assume when getting a surface from another process or API.
+ * If we have a modifier which supports compression, then the auxiliary data
+ * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
+ * can be in any of the following:
+ *
+ * - ISL_AUX_STATE_CLEAR
+ * - ISL_AUX_STATE_PARTIAL_CLEAR
+ * - ISL_AUX_STATE_COMPRESSED_CLEAR
+ * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
+ * - ISL_AUX_STATE_RESOLVED
+ * - ISL_AUX_STATE_PASS_THROUGH
+ *
+ * If the modifier does not support fast-clears, then we are guaranteed
+ * that the surface is at least partially resolved and the first three not
+ * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
+ * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
+ * because they are the least common denominator of the set of possible aux
+ * states and will yield a valid interpretation of the aux data.
+ *
+ * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
*/
static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)
if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
return ISL_AUX_STATE_AUX_INVALID;
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
}
return e;
}
+bool isl_color_value_is_zero(union isl_color_value value,
+ enum isl_format format);
+
bool isl_color_value_is_zero_one(union isl_color_value value,
enum isl_format format);
+static inline bool
+isl_swizzle_is_identity(struct isl_swizzle swizzle)
+{
+ return swizzle.r == ISL_CHANNEL_SELECT_RED &&
+ swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
+ swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
+ swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
+}
+
+bool
+isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
+ struct isl_swizzle swizzle);
+
+struct isl_swizzle
+isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
+struct isl_swizzle
+isl_swizzle_invert(struct isl_swizzle swizzle);
+
#define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) { __VA_ARGS__ });
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *ccs_surf,
- uint32_t row_pitch /**< Ignored if 0 */);
+ uint32_t row_pitch_B /**< Ignored if 0 */);
#define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
* Pitch between vertically adjacent surface elements, in bytes.
*/
static inline uint32_t
-isl_surf_get_row_pitch(const struct isl_surf *surf)
+isl_surf_get_row_pitch_B(const struct isl_surf *surf)
{
- return surf->row_pitch;
+ return surf->row_pitch_B;
}
/**
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
- return surf->row_pitch / (fmtl->bpb / 8);
+ assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
+ return surf->row_pitch_B / (fmtl->bpb / 8);
}
/**
static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf *surf)
{
- return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
+ return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
}
/**
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t bpb,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
enum isl_format format,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_sa,
uint32_t total_y_offset_sa,
uint32_t *base_address_offset,
const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
- isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
+ isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
total_x_offset, total_y_offset,
base_address_offset,
x_offset_sa, y_offset_sa);
projects / mesa.git / blobdiff