ISL_FORMAT_GEN9_CCS_64BPP,
ISL_FORMAT_GEN9_CCS_128BPP,
+ /* An upper bound on the supported format enumerations */
+ ISL_NUM_FORMATS,
+
/* Hardware doesn't understand this out-of-band value */
ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
};
struct isl_channel_layout {
enum isl_base_type type;
+ uint8_t start_bit; /**< Bit at which this channel starts */
uint8_t bits; /**< Size in bits */
};
* always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
* its physical size is 128B x 32rows, the same as a Y-tile.
*
- * @see isl_surf::row_pitch
+ * @see isl_surf::row_pitch_B
*/
struct isl_extent2d phys_extent_B;
};
uint32_t samples;
/** Lower bound for isl_surf::alignment, in bytes. */
- uint32_t min_alignment;
+ uint32_t min_alignment_B;
/**
* Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
* will fail if this is misaligned or out of bounds.
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
isl_surf_usage_flags_t usage;
uint32_t samples;
/** Total size of the surface, in bytes. */
- uint64_t size;
+ uint64_t size_B;
/** Required alignment for the surface's base address. */
- uint32_t alignment;
+ uint32_t alignment_B;
/**
* The interpretation of this field depends on the value of
* isl_tile_info::physical_extent_B. In particular, the width of the
- * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
+ * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
* and the distance in bytes between vertically adjacent tiles in the image
- * is given by row_pitch * isl_tile_info::physical_extent_B.height.
+ * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
*
* For linear images where isl_tile_info::physical_extent_B.height == 1,
* this cleanly reduces to being the distance, in bytes, between vertically
*
* @see isl_tile_info::phys_extent_B;
*/
- uint32_t row_pitch;
+ uint32_t row_pitch_B;
/**
* Pitch between physical array slices, in rows of surface elements.
/**
* The size of the buffer
*/
- uint64_t size;
+ uint64_t size_B;
/**
* The Memory Object Control state for the filled surface state.
*/
enum isl_format format;
- uint32_t stride;
+ uint32_t stride_B;
};
struct isl_depth_stencil_hiz_emit_info {
static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)
{
+ assert(fmt != ISL_FORMAT_UNSUPPORTED);
+ assert(fmt < ISL_NUM_FORMATS);
return &isl_format_layouts[fmt];
}
static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)
{
- return isl_format_layouts[fmt].name;
+ return isl_format_get_layout(fmt)->name;
}
bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
static inline bool
isl_format_is_srgb(enum isl_format fmt)
{
- return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
+ return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
}
enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
{
if (isl_format_is_yuv(fmt))
return false;
- return isl_format_layouts[fmt].channels.r.bits > 0 &&
- isl_format_layouts[fmt].channels.g.bits > 0 &&
- isl_format_layouts[fmt].channels.b.bits > 0 &&
- isl_format_layouts[fmt].channels.a.bits == 0;
+
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits == 0;
+}
+
+static inline bool
+isl_format_is_rgbx(enum isl_format fmt)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
+
+ return fmtl->channels.r.bits > 0 &&
+ fmtl->channels.g.bits > 0 &&
+ fmtl->channels.b.bits > 0 &&
+ fmtl->channels.a.bits > 0 &&
+ fmtl->channels.a.type == ISL_VOID;
}
enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
+enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
+
+void isl_color_value_pack(const union isl_color_value *value,
+ enum isl_format format,
+ uint32_t *data_out);
+void isl_color_value_unpack(union isl_color_value *value,
+ enum isl_format format,
+ const uint32_t *data_in);
bool isl_is_storage_image_format(enum isl_format fmt);
isl_surf_get_ccs_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *ccs_surf,
- uint32_t row_pitch /**< Ignored if 0 */);
+ uint32_t row_pitch_B /**< Ignored if 0 */);
#define isl_surf_fill_state(dev, state, ...) \
isl_surf_fill_state_s((dev), (state), \
* Pitch between vertically adjacent surface elements, in bytes.
*/
static inline uint32_t
-isl_surf_get_row_pitch(const struct isl_surf *surf)
+isl_surf_get_row_pitch_B(const struct isl_surf *surf)
{
- return surf->row_pitch;
+ return surf->row_pitch_B;
}
/**
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
- return surf->row_pitch / (fmtl->bpb / 8);
+ assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
+ return surf->row_pitch_B / (fmtl->bpb / 8);
}
/**
static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf *surf)
{
- return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
+ return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
}
/**
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t bpb,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
enum isl_format format,
- uint32_t row_pitch,
+ uint32_t row_pitch_B,
uint32_t total_x_offset_sa,
uint32_t total_y_offset_sa,
uint32_t *base_address_offset,
const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
- isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
+ isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
total_x_offset, total_y_offset,
base_address_offset,
x_offset_sa, y_offset_sa);
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