intel/isl: Remove 'inline' keywords

[mesa.git] / src / intel / isl / isl_emit_depth_stencil.c

diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 339da28bb8453365b193221bf015d1a94cf42dac..90ce8893e5b70db77846848480d370bac735c82f 100644 (file)
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -26,7 +26,7 @@
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
-static inline uint64_t
+static uint64_t
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 {
    return addr + delta;
@@ -37,10 +37,6 @@ __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 
 #include "isl_priv.h"
 
-#define __PASTE2(x, y) x ## y
-#define __PASTE(x, y) __PASTE2(x, y)
-#define isl_genX(x) __PASTE(isl_, genX(x))
-
 static const uint32_t isl_to_gen_ds_surftype[] = {
 #if GEN_GEN >= 9
    /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
@@ -113,6 +109,16 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
 #endif
    }
 
+#if GEN_GEN == 5 || GEN_GEN == 6
+   const bool separate_stencil =
+      info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
+   if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
+      assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
+      db.SeparateStencilBufferEnable = true;
+      db.HierarchicalDepthBufferEnable = true;
+   }
+#endif
+
 #if GEN_GEN >= 6
    struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
       GENX(3DSTATE_STENCIL_BUFFER_header),
@@ -151,9 +157,6 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
           info->hiz_usage == ISL_AUX_USAGE_HIZ);
    if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
       db.HierarchicalDepthBufferEnable = true;
-#if GEN_GEN == 5 || GEN_GEN == 6
-      db.SeparateStencilBufferEnable = true;
-#endif
 
       hiz.SurfaceBaseAddress = info->hiz_address;
       hiz.HierarchicalDepthBufferMOCS = info->mocs;