anv: Properly cache brw_stage_prog_data::relocs

[mesa.git] / src / intel / isl / isl_gen6.h

diff --git a/src/intel/isl/isl_gen6.h b/src/intel/isl/isl_gen6.h
index 99b0b77668bccc707c30320dbb3493c217c7af3e..c954026efb6468f63aded16859db3009f69426b2 100644 (file)
--- a/src/intel/isl/isl_gen6.h
+++ b/src/intel/isl/isl_gen6.h
@@ -21,9 +21,10 @@
  *  IN THE SOFTWARE.
  */
 
-#pragma once
+#ifndef ISL_GEN6_H
+#define ISL_GEN6_H
 
-#include "isl_priv.h"
+#include "isl.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -46,3 +47,5 @@ isl_gen6_choose_image_alignment_el(const struct isl_device *dev,
 #ifdef __cplusplus
 }
 #endif
+
+#endif /* ISL_GEN6_H */