anv/blorp: Turn off AUX after doing a CCS_D resolve

[mesa.git] / src / intel / isl / isl_gen7.c

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 022dd866a74f9ee24138a0b5f308209e36cbe273..18687b535def99497c2790c16427e22a960fe280 100644 (file)
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -25,10 +25,10 @@
 #include "isl_priv.h"
 
 bool
-gen7_choose_msaa_layout(const struct isl_device *dev,
-                        const struct isl_surf_init_info *info,
-                        enum isl_tiling tiling,
-                        enum isl_msaa_layout *msaa_layout)
+isl_gen7_choose_msaa_layout(const struct isl_device *dev,
+                            const struct isl_surf_init_info *info,
+                            enum isl_tiling tiling,
+                            enum isl_msaa_layout *msaa_layout)
 {
    bool require_array = false;
    bool require_interleaved = false;
@@ -155,9 +155,7 @@ static bool
 gen7_format_needs_valign2(const struct isl_device *dev,
                           enum isl_format format)
 {
-   /* This workaround applies only to gen7 */
-   if (ISL_DEV_GEN(dev) > 7)
-      return false;
+   assert(ISL_DEV_GEN(dev) == 7);
 
    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
     * RENDER_SURFACE_STATE Surface Vertical Alignment:
@@ -184,9 +182,9 @@ gen7_format_needs_valign2(const struct isl_device *dev,
  * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
  */
 void
-gen6_filter_tiling(const struct isl_device *dev,
-                   const struct isl_surf_init_info *restrict info,
-                   isl_tiling_flags_t *flags)
+isl_gen6_filter_tiling(const struct isl_device *dev,
+                       const struct isl_surf_init_info *restrict info,
+                       isl_tiling_flags_t *flags)
 {
    /* IVB+ requires separate stencil */
    assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
@@ -217,6 +215,12 @@ gen6_filter_tiling(const struct isl_device *dev,
       *flags &= ~ISL_TILING_W_BIT;
    }
 
+   /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
+    *    If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
+    */
+   if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC)
+      *flags &= ISL_TILING_Y0_BIT;
+
    /* MCS buffers are always Y-tiled */
    if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
       *flags &= ISL_TILING_Y0_BIT;
@@ -249,9 +253,13 @@ gen6_filter_tiling(const struct isl_device *dev,
        *   For multisample render targets, this field must be 1 (true). MSRTs
        *   can only be tiled.
        *
-       * Multisample surfaces never require X tiling, and Y tiling generally
-       * performs better than X. So choose Y. (Unless it's stencil, then it
-       * must be W).
+       * From the Broadwell PRM >> Volume2d: Command Structures >>
+       * RENDER_SURFACE_STATE Tile Mode:
+       *
+       *   If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
+       *   must be YMAJOR.
+       *
+       * As usual, though, stencil is special and requires W-tiling.
        */
       *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
    }
@@ -380,13 +388,15 @@ gen7_choose_valign_el(const struct isl_device *dev,
 }
 
 void
-gen7_choose_image_alignment_el(const struct isl_device *dev,
-                               const struct isl_surf_init_info *restrict info,
-                               enum isl_tiling tiling,
-                               enum isl_dim_layout dim_layout,
-                               enum isl_msaa_layout msaa_layout,
-                               struct isl_extent3d *image_align_el)
+isl_gen7_choose_image_alignment_el(const struct isl_device *dev,
+                                   const struct isl_surf_init_info *restrict info,
+                                   enum isl_tiling tiling,
+                                   enum isl_dim_layout dim_layout,
+                                   enum isl_msaa_layout msaa_layout,
+                                   struct isl_extent3d *image_align_el)
 {
+   assert(ISL_DEV_GEN(dev) == 7);
+
    /* Handled by isl_choose_image_alignment_el */
    assert(info->format != ISL_FORMAT_HIZ);