anv: Move nir_lower_wpos_center after dead variable elimination.

[mesa.git] / src / intel / isl / isl_gen7.c

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 76213f814a50ce13a940868628eb2a32a7b08b20..18687b535def99497c2790c16427e22a960fe280 100644 (file)
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -155,9 +155,7 @@ static bool
 gen7_format_needs_valign2(const struct isl_device *dev,
                           enum isl_format format)
 {
-   /* This workaround applies only to gen7 */
-   if (ISL_DEV_GEN(dev) > 7)
-      return false;
+   assert(ISL_DEV_GEN(dev) == 7);
 
    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
     * RENDER_SURFACE_STATE Surface Vertical Alignment:
@@ -217,6 +215,12 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
       *flags &= ~ISL_TILING_W_BIT;
    }
 
+   /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
+    *    If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
+    */
+   if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC)
+      *flags &= ISL_TILING_Y0_BIT;
+
    /* MCS buffers are always Y-tiled */
    if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
       *flags &= ISL_TILING_Y0_BIT;
@@ -391,6 +395,8 @@ isl_gen7_choose_image_alignment_el(const struct isl_device *dev,
                                    enum isl_msaa_layout msaa_layout,
                                    struct isl_extent3d *image_align_el)
 {
+   assert(ISL_DEV_GEN(dev) == 7);
+
    /* Handled by isl_choose_image_alignment_el */
    assert(info->format != ISL_FORMAT_HIZ);